搜索资源列表
control0
- systemverilog编写的cpu读写mem程序-SystemVerilog prepared by the cpu readers mem procedures
fifo0
- systemverilog编写的fifo例子-SystemVerilog examples prepared by the fifo
SVDrink
- Systemverilog 编写的贩卖机代码-Systemverilog preparation for the sale code
SystemVerilog_FIFO_Channel
- 2004 SNUG of systemverilog
snug06_cohen_sri_aji.tar
- VMMforSystemVerilog的源码资料 学习SystemVerilog的好东西
22SystemVerilog
- SystemVerilog 介绍 对初学者很有好处
hdl
- 对 VHDL Verilog 和Systemverilog的详细对比，对与初学者十分有益！
Comparison_of_VHDL_Verilog_and_SystemVerilog
- Comparison of VHDL Verilog and SystemVerilog
systemverilog
- 这是一本关于verilog编程语言的教程,对学习verilog语言有帮助
ovm-1.1.tar
- ovm的包，主要应用于systemverilog验证-ovm the package, mainly used to verify systemverilog
sva_assetion
- 学习SVA的最基本的例子，对于想了解systemverilog assertion的相关人员非常有用！-SVA learn the most basic example, the systemverilog assertion would like to know the person very useful!
Based-SystemVerilog-ofAMBA-Bus
- 本论文是基于systemverilog的AMBA总线的实现，是学习systemverilog的一份好资料-This paper is based on systemverilog AMBA bus implementation, is to learn systemverilog a good information
Writing-TBusing-SystemVerilog
- 本书是关于如何用systemverilog写测试台程序的，对于搞验证和测试的人绝对有用-This book is about how to use the systemverilog write test bench program, for those who engage in verification and testing is absolutely useful
SystemVerilog 验证方法学
- systemverilog 验证方法学，夏宇闻版(systemverilog verification methodology)
SystemVerilog
- 有三篇systemVerilog的经典书，对学习很有帮助(There are three classic books of SystemVerilog, helpful for learning)
THE_UVM_PRIMER_CODE_EXAMPLES.tar
- The exmaples for the ebook The UVM Primer An Introduction to the Universal Verification Methodology by Ray Salemi The UVM Primer is the book to read when you've decided to learn the UVM. The book assumes that you have a basic knowledge of SystemVeri
SystemVerilog断言及其应用
- 该书用来阐述如何使用断言，以及断言的语法和示例(The book is devoted to the use of assertions, as well as to the syntax and examples of assertions)
SystemVerilog 3.1a中文+英文版
- Sytem Verilog 语言的设计事项(SystemVerilog user Guide)
SystemVerilog for Design(Second Edition)
- 本文档用于使用systemverilog系统硬件描述语言做ASIC设计，深入浅出，易懂(The doc is using systemverilog system harward descr iption language to do ASIC design.The doc is easy to read,for new bird in this fact.)
systemverilog+assertions应用指南
- system verilog assertion介绍(system verilog assertion introduction)