搜索资源列表
memoryarray
- 由VHDL撰写的两记忆体转置程序，内含testbench与转置源码。-VHDL written by the two memory migration procedures, includes testbench and migration source.
des
- des解密加密的verilog源代码其中包含有测试源代码，仿真结果图-verilog des decrypt encrypted source code which includes testing the source code, Simulation results
counter
- 计数器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about counter for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
arm9verilog
- AMBA AHB verilog Source code
elevator_controller
- vhdl elevator controller with testbench
code
- 一个基于fpga的简单的实时心电检测系统，包括与pc通讯和qrs检测两部分-A simple fpga-based real-time ECG detection system, including communication with the pc and qrs detection of two parts
uart2bus_latest.tar
- 文档详尽、已验证的UART工程，含有testbench文件。采用VHDL、Verilog语言编写。-Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.
AES_enc_core_tb
- this code discribers testbench for aes algorithm. it is written by .vhdl
ALU
- VHDL实现ALU的源代码，并且提供了一个详细的testbench-ALU VHDL source code implementation, and provides a detailed testbench
VHDL_Somador8Bits
- * FullAdder implementation in VHDL with respectives signals: a, b : in std_logic_vector (7 downto 0) soma : out std_logic_vector (7 downto 0) ci : in std_logic co : out std_logic overflow : out std_logic negativo : out std_logic
lab1a
- 这个是一个简单的VHDL testbench程序，让你简单清楚的了解如何写一个testbench-this is a simple vhdl testbench program, it is very easy for you to understand how to write a testbench program
ReadFsm
- VHDL小程序，read FSM。可以作为VHDL一次作业使用。包含测试文档testbench。-VHDL applet, read FSM. A job can be used as a VHDL。VHDL code and testbench.
decoder
- It is a simple decoder created using vhdl in xilinx ise.It will helpful for beginners to create deocder using this.testbench for simulation is also created.
Multiplieur-signe
- VHDL code of a signed mixer with a testbench !
74serie-code
- 74系列的源代码 里面还包含了testbench和详细的代码说明-Prepared by flash controller vhdL source code. Contains testbench. Programming Language:VHDL, Tags:VHDL-FPGA-Verilog,
8051_latest.tar
- 8051 Rev 0.2 OpenCores VHDL core with testbench
serialdivider-model
- this is serial divider model vhdl file and testbench not included
pci_code
- PCI接口程序，采用VHDL语言，包括主程序和testbench文件-PCI INTERFACE IN VHDL
spi_master
- 用VHDL编写的一个SPI主机程序，SPI模块采用最常用的模式0方式（即CPOL=0,CPHA=0）通信。文件内含测试文档，已在Modelsim6.5上测试通过，可在FPGA上直接调用。-A SPI Master code edited by VHDL language,the SPI modul use 0 MODE(i.e CPOL=0,CPHA=0)to communicate with the SPI Slave.and there is a testbench in the file
vhld_tb_latest.tar
- 一个VHDL的测试平台，可以用来验证MircroProcessor，有完备的文档和代码。-A testbench based on VHDL language, you can apply it to verify a simple mircroprocessor, include complete ducoment and sources