搜索资源列表
uart
- 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
fpga_uartrw
- FPGA的uart控制器的verilog源程序,在cyclone II EP2C8Q208上调试运行成功-FPGA s UART controller Verilog source code, in cyclone II EP2C8Q208 debugging run successfully
UART_for_FPGArar
- it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state machine based UART and it wll
UART
- 简易UART程序 verilog 描述-Simple UART procedure described in verilog
UART
- 用FPGA开发的串口通信的程序,代码是用verilog编写的,希望对大家有用!-Serial communication with the FPGA development process, the code is written in verilog and hope for all of us!
UART
- the uart transmitter and receiver are used to design the data transmission for 8bit sipo and piso in verilog
uart
- the uart model is used to design the synthies and beherival model in verilog fpga
uart_rx
- Tcode is in VERILOG HDL (Hardware descr iption language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL
UART_IP_core_for_wishbone
- 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
RS232
- It s combination logic for UART. edited in verilog-HDL
RS232
- It s combination logic for UART. Edited in verilog-HDL.
uart
- 关于串口发送的verilog代码,实验中经常用到,已经用FIFO-it is about the uart transmit verilog code,very useful in experiment.
Uart
- UART source code in verilog
s24_uart
- 这是一个串口通信协议,有详细的说明,欢迎下载!-This a code of uart in verilog ,describled in detail,welcome to download!
1.UART
- 该代码主要实现UART的串行通信,针对的是RS232芯片,同时包含了verilog和VHDL编写的程序-The code UART serial communication, RS232 chip, also contains a program written in verilog and VHDL
uart-in-verilog
- develop uart using verilog language-develop uart using verilog language...
UART
- 用verilog编写的UART串口通信程序,经验证误码率为0,系统由ARM控制FPGA的串口进行通信;-Written in verilog UART serial communication procedures, proven error rate is 0, the system controlled by ARM FPGA serial communication
UART-Verilog-source
- Verilog编写UART串口例程,实现FPGA与上位机串口通信,利用ASCII码进行大小写转换,在Xilinx Virtex-5开发板测试通过-UART serial routines written in Verilog, FPGA serial communication with the host computer using the ASCII code case conversion, in the Xilinx Virtex-5 development board test
UART
- General purpose UART written in Verilog Libero core generator.-General purpose UART written in Verilog Libero core generator.
UART-master
- FPGA Based UART in Verilog