搜索资源列表
Verilog
- 各类verilog源代码 计数器，全加器，串行快等。-All verilog source code counter, adder, serial quick.
Lab1_solution
- 8bit adder. this is verilog file.
adder_csa
- carry select adder in verilog
FullAdder
- This a code programed in Verilog Language. It is Full Adder code designed using Half Adder-This is a code programed in Verilog Language. It is Full Adder code designed using Half Adder..
fpufiles
- floating point adder mul and sub in verilog code
adder
- 用verilog语言描述的二级加法器，通过在ise环境下编译成功。-With the verilog language to describe the two adders, compiled by ise environment successfully.
adder3
- 此源代码是基于Verilog语言的七人投票表决器 、2 个 8 位数相乘 、8 位二进制数的乘法 、同一循环的不同实现方式、使用了`include 语句的 16 位加法器 、条件编译、加法计数器中的进程、任务、测试、函数、用函数和 case语句描述的编码器、阶乘运算函数、测试程序 、顺序执行、并行执行，特别是七人投票表决器，这是我目前发现的最优的用硬件描述的源代码。-The Verilog language source code is based on the seven-vote, and
cla16
- 16位超前进位加法器的源代码，整个工程文件都有，是在ISE10.1下建立的，可以帮助理解超前进位原理（对了，是Verilog的，因为上面没看到只好选VHDL了）-16-bit look-ahead adder the source code files have the whole project was established under the ISE10.1 to help understand the lookahead principle (By the way, is the Ver
adder_fa4bit
- 4 bit full adder verilog code n test bench
Adder_Kogge_Stone_32bit_With_Test_Bench
- verilog source code and test bench of Adder Kogge Stone 32-Bit
Full.adder
- Verilog的RTL级别全加器和测试平台，测试通过-Verilog RTL level full adder and test benck
Gate.level.adder
- Verilog 门电路级别的全加器，测试通过-Verilog Gate Level adder and testbenck
16bit-CLA
- a 16 bit carry look ahead adder verilog code
serial_adder
- This is a simple Serial Adder for Quartus II. The source code is in verilog HDL
add32
- 32位加法器，基于vhdl语言，主要用于测试算法-32-bit adder, based on the vhdl language, mainly used for testing algorithms
verilog-programs
- These are first programs of my asic and fpgas lab.This folder contains simple half adder and its test bench using verilog language.Then it also contains 4 to 1 mux using two 2 to 1 muxes.Then its also has its test bench to check the code.These progra
adder
- actel fpga加法器的verilog源码，在libero环境开发的-actel fpga adder verilog source code, development environment in the libero
add32
- 32位加法器，verilog实现，且有仿真图像-32-bit adder and programed by veilog
ADDER
- verilog DHL编写的一位全加器，编译通过。稍作修改便可编程任意位加法器。-verilog DHL write a full adder, compiled by. Slight modifications can be programmed any adder.
Verilog
- 基于verilog HDL编写的各种实例。。里面记载了计数器，全加器，等等的代码。-Based on various examples written in verilog HDL. . Recording the counter, full adder, and so the code.