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用一位全加器组成四位全加器
- 用一位全加器组成四位全加器. 所用语言是Verilog HDL. 主要用在加法器的设计中。-All-Canadian with a composed four-adder. The language used is the Verilog HDL. In addition main The design.
source_verilog
- verilog shi 实现的加法器（8位）适用于初学asic -Verilog realized Adder (8) applies to beginners blends
CALCULAT.ZIP
- verilog源码，可实现两位的加法器，在xillinx foundation 3.1下验证通过-verilog source, the two can achieve Adder, In xillinx foundation 3.1 certification through
adder_ahead8bit
- 本文件提供了用verilog HDL语言实现的8位超前进位加法器,充分说明了超前进位加法器和普通加法器之间的区别.-using verilog HDL achieve the eight-ahead adder, fully demonstrates the CLA for ordinary Adder and the distinction between.
add_16_pipe
- 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
Verilog_Development_Board_Sources
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code q
LAC_adder16
- 十六位超前进位加法器，Verilog HDL-16-ahead adder, Verilog HDL
adder_Xilinx_Spartan_3
- 这是个基于 Xilinx Spartan3 的加法器，利用Verilog语言编写，对于EDA初学者来说有一定的参考价值。 -This is based on the Xilinx Spartan3 Adder, Verilog language use, EDA newcomer has some reference value.
89_full_adder
- full adder设计代码，verilog 语言描述，通过modelsim 仿真，quartus综合
cla_src
- carry lookahead adder verilog program
FULLADD
- Full adder using Verilog
acc32bit 本设计为32位数字相位累加器
- 本设计为32位数字相位累加器，门级描述的Verilog代码。其中，acc32bit.v为顶层文件，full_add1.v为一位全加器的门级描述模块，flop.v为触发器的门级描述模块。-The design for the 32-bit digital phase accumulator, gate-level descr iption of the Verilog code. Which, acc32bit.v as top-level file, full_add1.v as a full
waterline_adder.rar
- 这是一个用Verilog编写的四级流水线加法器,This is a Verilog prepared with four pipeline adder
add_tree_mult
- 8位加法树乘法器,实现两个8位二进制数相乘，采用verilog hdl-8-bit adder tree multiplier, the achievement of the two 8-bit binary number multiplied, using verilog hdl
c15_add
- 精通verilog HDL语言编程源码之1--常用加法器设计-Proficient in programming language source verilog HDL of 1- Common adder design
cla4
- verilog code 4-bit carry look-ahead adder output [3:0] s //summation output cout //carryout input [3:0] i1 //input1 input [3:0] i2 //input2 input c0 //前一級進位-verilog code4-bit carry look-ahead adderoutput [3:0] s// summationoutput cout// c
bitadder
- 一位全加器，VERILOG实现，包括测试文件，测试可用，欢迎下载，共同学习-A full adder, VERILOG implementation, including test papers, test available, please download, a common study
16_COMLEX ADDER
- Complex Numbers are denoted in the form a+ib where a is the real part and b is the imaginary part
lab0_32
- 大学生专业课的lab，用Verilog实现半加器(the necessary lab for college students to fulfill the function of half-adder)
BrentKung32
- 32 bit brent kung adder