搜索资源列表
Verilog-HDL
- Verilog HDL的基本语法的学习资料。-Verilog HDL the basic syntax.
ARM-Verilog-HDL-IP-CORE
- ARM Verilog HDL IP CORE， ARM IP核，采用verilog编写-ARM Verilog HDL IP CORE, ARM IP core, using verilog write
Verilog-HDL--MODEL
- Verilog HDL程序设计教程verolog代码设计，包含各种基本代码-Verilog HDL programming tutorial verolog code design, includes a variety of basic code
verilog-HDL-code
- Verilog HDL程序设计实例详解的源代码-verilog HDL code
7duanyimaguan-Verilog-HDL
- 7段译码管的Verilog HDL程序，希望对大家有用-7 segment decoder tube Verilog HDL procedures
CD-ROM-code-(verilog-hdl)
- 数字信号处理的fpga实现 第2版-光盘源码（verilog HDL）-Fpga implementation of digital signal processing 2nd Edition- CD source (verilog HDL)
verilog-hdl
- 本设计是以四路抢答为基本概念。从实际应用出发,利用电子设计自动化( EDA)技术,用可编程逻辑器件设计具有扩充功能的抢答器。它以Verilog HDL硬件描述语言作为平台，结合动手实验而完成的-The design is based on four basic concepts answer. From the practical application, the use of electronic design automation (EDA) technology, using a prog
Verilog.HDL
- <精通Verilog.HDL语言编程_源码>-< Proficient Verilog.HDL source programming language _>
Verilog.HDL
- 精通Verilog.HDL语言编程_源码，对初学者来说很好的值得借鉴-Proficient Verilog.HDL language programming _ source, good for beginners should learn
Verilog-HDL-washer
- 智能洗衣机控制器 基于verilog hdl状态机 具有多种功能切换-Intelligent washing machine controller verilog hdl-based state machine has multi-functional switch
Verilog-HDL--examples
- 王金明：《Verilog HDL 程序设计教程》书中的全部范例，pdf版本。-Wang Jinming: " Verilog HDL Programming Guide" all examples in the book, pdf version.
Verilog-HDL-basics-for-beginners
- Verilog HDL的基础知识,适合初学者阅读-Verilog HDL basics for beginners to read
Verilog-HDL-for-entering-Huawei
- Verilog HDL 华为入门教程 想去华为的可以学习下-Verilog HDL want Huawei Huawei introductory tutorial can learn under
Verilog-HDL
- 本课程设计在EDA开发平台上利用Verilog HDL语言设计数控分频器电路，利用数控分频的原理设计乐曲硬件演奏电路，并定制LPM-ROM存储音乐数据，-This course is designed to take advantage of the EDA Verilog HDL language development platform NC divider circuit design, the use of CNC dividing principles music playing ha
Verilog-HDL-introduction
- 简单实用的Verilog HDL 入门教程-Verilog HDL introduction
vga显示实验及代码
- 里面有具体的关于VGA显示的实验说明及代码，基于verilog HDL语言，里面有三个实验及代码
seg7
- verilog HDL编写的FPGA定时器并用数码管显示(Verilog HDL prepared by the FPGA timer and digital display)
Verilog数字系统设计教程
- Verilog教程 数字系统设计 夏宇闻(Verilog Digital System Design)
cnt12
- 十二进制计数器，基于verilog HDL实现。(Twelve decimal counter)
mux_2to1_4to1_8to1
- design verilog hdl for mux 2to1, mux4to1, mux8to1