搜索资源列表
rs232
- fpga的串口读写程序，经硬件测试成功，波特率9600.可以改变分频值适应不同的时钟和波特率-fpga serial read and write procedures, by the hardware to test the success of 9600 baud rate. frequency value can be changed to adapt to a different clock and baud rate
clk_vhdl
- Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
rs232_VHDL
- RS232 uart的VHDL实现，包括时钟分频（波特率产生），接收，发送-Implement of RS232 uart in VHDL
fq_div
- pll 的64倍频 锁相环技术用 实现倍频 从而达到对频率的分频-pll 64 multiplier PLL multiplier used to achieve so as to achieve the sub-band of frequencies
jtdvhdl
- 自己做的VHDL交通灯控制器；分频器、信号控制器、时钟模块；EDA； 通过了仿真、运行。时间可以设置为随意的两位数.-code and jpf
chengxu
- 一个分频器，一个卷积编码器的程序，都是VDHL的-A frequency divider, a convolutional encoder program, are VDHL of
Fredevider_n
- 任意N偶数倍频率分频器VHDL语言，编译器MAX_PLUS2-Any even multiple of the frequency divider N VHDL language, compiler MAX_PLUS2
vhdl-examples
- VHDL写的100多个经典例子，适合初学者。包括分频器，简易时钟等-VHDL written more than 100 classic example, suitable for beginners. Divider, the simple clock
CyclonePLL
- Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟
1
- 根据交通灯控制器的功能与要求，将其总体电路分为分频器、信号控制器两个模块。-According to the traffic light controller functions and the requirements of the overall circuit is divided into its divider, the signal controller two modules.
VHDL
- 1 8位加法器的设计 2 分频电路 3 数字秒表的设计-1 8 adder design of 2-circuit design of 3 digital stopwatch
3fp
- 奇数分频和倍频(只需修改参数就可以实现较难得基数分频和倍频)-Odd frequency and frequency-doubling (just modify the parameters can be achieved relatively rare sub-base frequency and octave)
fen1to7
- 这是我在ISP编程实验中独立编写的一个采用行为描述方式实现的分频器，通过两个并行进程对输入信号CLK进行8分频，占空比为1:7-This is my ISP programming experiment in the preparation of an independent descr iption of the use of behavior to achieve the prescaler, through two parallel processes on the input signa
CLK_DIV
- 爱用硬件描述语言VHDL实现输入时钟10分频输出-divide CLOCK by 10 using VHDL
hz
- 万能频率器，可以修改其中的参数，可是实现任意的分频！很方便！-Universal frequency, you can modify one of the parameters, but any implementation of the sub-band! Very convenient!
ADC0809VHDL
- 文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Descr ipt