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e3
- 4位可逆计数器:将50MHz的时钟进行 分频后的结果作为时钟控制,根据输入进行条件判断,再通过设置一个四位的向量将结果输出,利用数码管显示在实验板上-CNTR 4: will be conducted at 50MHz clock frequency as the clock after the control conditions to determine the basis of inputs, and then set up a four through the results of th
EDAkechengsheji
- 实现6位频率计,防止数据溢出,并对频率进行三分频-Frequency to achieve 6 to prevent data overflow, and one-third of the frequency band
VHDL
- 多路分频及周期检测 端口映射示例程序-descr iption
clk_div
- VHDL语言描述,时钟分频,给定CPLD试验板系统时钟设置50M,但由于本作品的需要,我们将系统时钟经过20分频得到DS18B20所需的工作时钟,大约为1.25M。-VHDL language descr iption, the clock frequency, a given CPLD experiment board system clock set 50M, but as a result of this work, we will be the system clock frequenc
times
- 计数器,用VHDL实现,先6分频,再10分频,24分频,同时可做万年历-Counter, using VHDL realization frequency first 6 hours, 10 minutes and then the frequency, frequency of 24 minutes, at the same time to do calendar
serialcomvhdl
- 一个串行通信的例子,用vhdl实现。包括发送接收,分频等多个模块-Example of a serial communication with the realization of vhdl. Including the transmission of the reception, a number of modules, such as Frequency Division
ADC0809VHDL
- 8.4 ADC0809 VHDL控制程序 见随书所附光盘中文件:ADC0809VHDL程序与仿真。 --文件名:ADC0809.vhd --功能:基于VHDL语言,实现对ADC0809简单控制 --说明:ADC0809没有内部时钟,需外接10KHz~1290Hz的时钟信号,这里由FPGA的系 --统时钟(50MHz)经256分频得到clk1(195KHz)作为ADC0809转换工作时钟。 --最后修改日期:2004.3.20 -8.4 ADC0809 VHDL con
clock
- 由锁相环(PLL)产生所需的2分频与4分频时钟8分频时钟 clk.qpf为可执行主程序 -By the phase-locked loop (PLL) have the necessary 2-and 4-frequency clock frequency of 8 minutes for Executable clk.qpf main clock
VHDL
- 基于vhdl数控分频器的设计与应用,少有的关于分频方法的介绍-Divider based on vhdl design and application of NC
signal_output
- 本文件是可以直接使用下载到FPGA里面使用,里面包含时钟分频电路,串并转换和并串转换电路,多通道信号加权的乘加电路等。-The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation
dianziqin
- 这个程序是利用Quartus II编写的利用数控分频器设计硬件电子琴,主系统由3个模块组成,顶层设计文件内部有三个功能模块:SPEAKER.VHD 和TONE.VHD和NoteTabs.vhd。模块TONE是音阶发生器,模块SPEAKER中的主要电路是一个数控分频器,NOTETABS模块用于产生节拍控制和音阶选择信号。-This program is the use of Quartus II design prepared by the use of CNC divider hardware
VHDLfenpin
- VHDL进行分频的完备资料,包含偶数、奇数、小数、分数-VHDL for the completeness of the information divide, including even and odd numbers, decimals, fraction
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一,尽管在目前大部分设计中,广泛使用芯片厂家集成的锁相环资源,如altera 的PLL,Xilinx的DLL.来进行时钟的分频,倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
VHDL
- 分频跑马灯数码管示范代码能实现分频跑马灯数码管示范-Crossover Marquee digital control Model Code
jifei
- 在Quartus环境中,采用VHDL语言编写的出租车计费系统,系统共分为分频、状态切换、记程、计费等模块,模仿现实中出租车计费。-In the Quartus environment, the use of VHDL language taxi billing system, the system is divided into sub-frequency, state switching, recording process, billing and other modules, to imi
music_disply
- 音乐播放器 中的数控分频器 后续还需要添加一个分频的电路-Music player in the follow-up of NC divider also need to add a sub-frequency circuit
uart
- RS232控制分频,实现占空比和频率可以控制的分频器-verilog RS232
DigitalClock
- 基于FPGA的数字电子钟设计,系统总程序由分频模块、“时分秒”计数器模块、数据选择模块、报时模块、动态扫描显示和译码模块组成。得到一个将“时”、“分”、“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时,显示满刻度为23时59分59秒,另外有校时、校分和整点报时功能,并通过数码管驱动电路显示计时结果。-FPGA-based design of digital electronic clock, the system program by the total frequency modul
clk_div
- 分频计数器verilog源代码,包括实验说明文档,清晰易懂.-this code can easily be understood and teaches you how to divide the clock.