搜索资源列表
347
- SDRAM的控制器的VHDL语言编写代码
AlteraSdramIP
- Altera Sdram IP 源码,VHDL写的
sdRAM设计及源代码(vhdl)
- 通过对不读数据的不断刷新来保持数据,通过地址线复用来传输数据。
ddr_sdram_controller_vhdl.rar
- DDR SDRAM控制器的VHDL代码已经测试,DDR SDRAM controller VHDL code
sdramcontroller.rar
- FPGA读写SDRAM的VHDL程序(已经测试过),SDRAM read and write the VHDL program FPGA (already tested)
sdram_vhdl_lattice
- sdram接口的vhdl实现,适用于lattice的FPGA,内含状态机和各个模块的具体实现-SDRAM interface VHDL realization lattice applied to the FPGA, containing the state machine and the concrete realization of each module
pingpang
- 关于乒乓操作的,对于数据缓存有很大的用处-On the ping-pong operation of data cache for the great usefulness of
SDRAM_CTR
- vhdl语言编写的fpga控制sdram的程序,包括仿真结果.-program of vhdl to control sdram in which includes the simulating results
ctrller
- 本代码是控制SDRAM的VHDL代码,几经优化现已趋近完美,里面主要用状态机实现,现封装为entity,便于调用模块-This code is to control the SDRAM of the VHDL code, optimization has been several times closer to perfection, which is mainly used to achieve a state machine is encapsulated entity, easy to c
sdram_vhdl
- VHDL实现的读取和写入SDRAM的程序代码,学习的人可以参考下-VHDL implementation SDRAM read and write program code, can refer to the following study
pudn
- VHDL写的SDRAM的精简控制器。包含SDRAM接口控制器,和数据读写控制。含有实际抓取的signatap波形。为初学SDRAM者的,最好参考。-A SDRAM controller written in VHDL.Including SDRAM interface controller, read and write control. It is the best reference for SDRAM learners .
Command
- sdram控制器命令接口模块的VHDL源程序文件,可直接用-sdam command model
pll1
- sdram控制器pll命令接口模块的VHDL源程序文件,可直接用-sdram pll
sdr_data_path
- sdram控制器data_path命令接口模块的VHDL源程序文件,可直接用-sdram data_path
sdr_sdram
- sdram控制器顶层模块的VHDL源程序文件,可直接用-sdr SDRAM
sdram_vhdl_lattice
- SDRAM控制器:基于VHDL语言的SDRAM控制器-SDRAM controller: SDRAM controller based on VHDL language
a12
- FPGA读写SDRAM的VHDL程序(已经测试过)-FPGA SDRAM read and write the VHDL program (already tested)
sdram_controller
- sdram controller written in vhdl and tested
ddr_code
- 基于FPGA的DDR SDRAM控制器的VHDL硬件描述语言-FPGA-based DDR SDRAM controller VHDL hardware descr iption language
DDRSDRAM
- 用vdhl编写的DDR sdram控制器,采用模块化编写,条理清楚,注解详细,附有存储器的说明。-the ddr sdram controller base vhdl