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用VHDL语言实现的序列检测器 （以1010111为例）-Sequence detector (for example 1010111)
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VHDL中序列检测器的设计的实验报告，包括源代码-VHDL in the design of sequence detector test reports, including the source code
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用VHDL语言实现一个序列检测器，检测到规定的序列时输出一高电平-VHDL language used to implement a sequence detector, to detect the sequence provided a high level when the output of
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序列信号发生器与检测器设计：用状态机设计实现串行序列检测器的设计，先设计（可用原理图输入法）序列信号发生器产生序列：0111010011011010；再设计检测器，若检测到串行序列11010则输出为“1”，否则输出为“0”，并对其进行仿真和硬件测试。-Sequence signal generator and detector design: The Design and Implementation of a serial sequence of state machine design of
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vhdl program for random access memory and sequence detector
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1、根据设计要求，完成对序列信号检测器的设计。
2、进一步加强对QuartusⅡ的应用和对VHDL语言的使用。-1, according to design requirements, to complete the sequence of the signal detector design. 2, to further strengthen the Quartus Ⅱ applications and the use of the VHDL language.
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以VHDL设计一有限状态机构成的序列检测器。序列检测器是用来检测一组或多组序列信号的电路，要求当检测器连续收到一组串行码（如1110010）后，输出为1，否则输出为0。-With VHDL Design into a finite state machine sequence detector. Sequence detector is used to detect the signal sequence of one or more groups of circuits, require th
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状态机的VHDL实现，在quartus-ii7.2上测试通过，文件包括米利状态机，摩尔状态机，ADC0809的状态机实现，序列检测器和定时去毛刺的状态机实现。-State machine code in VHDL,successfully tested in quartus-ii7.2,the file contains mealy state machine,moore state machine,ADC 0809 and sequence detector achieved in state
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用VHDL语言，设计一个“101”序列检测器，双过程描述编写-VHDL language, to design a dual procedure describes the preparation of "101" sequence detector.
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这个程序就是序列检测器的vhdl实现，真麻烦啊-This program is the sequence detector vhdl achieve real trouble
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FPGA环境下，用VHDL语言实现序列脉冲器和检测器。-FPGA environment, the use of the VHDL sequence of pulses and detector.
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基于VHDL语言实现的序列检测器，包含按键防抖动功能的实现。-Sequence detector based on the VHDL language, containing the button shake function to achieve.
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ise13.2环境下VHDL编写的8位序列检测器+仿真波形-ise13.2 environment in VHDL 8 sequence detector+ simulation waveforms
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vhdl 语言实现序列检测器 -vhdl language sequence detector vhdl language sequence detector
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1101序列检测器，VHDL编写，外部输入任意序列，一旦检测到1101就亮led提示。-1101 sequence detector, VHDL prepared, external input arbitrary sequence, once detected 1101 bright LED tips.
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先设计序列发生器产生序列：1011010001101010；再设计序列检测器，检测序列发生器产生序列，若检测到信号与预置待测信号相同，则输出“1”，否则输出“0”，并且将检测到的信号的显示出来。-First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is dete
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本源码是基于VHDL语言环境下的基础实验源码，共分七个部分。分别是：序列检测器、数字密码锁、四位有符号数除法、同步FIFO、DPLL的设计以及Cordic 算法实现。对于VHDL的初学者具有极大的参考价值。-The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, di
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Code on Debouncer, ripple carry adder, Sequence detector, huffmann encoder and some more examples in VHDL
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VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 prio
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VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. It includes 3 line -8 line decoder, 4 selector 1 selector, 6 elevator, 8 line -3 encoder, 8 l
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