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VHDLTESTBENCH
- 本文档对编写vhdl的testbench具有很大的参考价值，偶那个多方面考虑的-The preparation of this document, the testbench vhdl of great reference value, even considering that many
AES_enc_core_tb
- this code discribers testbench for aes algorithm. it is written by .vhdl
ALU
- VHDL实现ALU的源代码，并且提供了一个详细的testbench-ALU VHDL source code implementation, and provides a detailed testbench
VHDL_Somador8Bits
- * FullAdder implementation in VHDL with respectives signals: a, b : in std_logic_vector (7 downto 0) soma : out std_logic_vector (7 downto 0) ci : in std_logic co : out std_logic overflow : out std_logic negativo : out std_logic
ReadFsm
- VHDL小程序，read FSM。可以作为VHDL一次作业使用。包含测试文档testbench。-VHDL applet, read FSM. A job can be used as a VHDL。VHDL code and testbench.
decoder
- It is a simple decoder created using vhdl in xilinx ise.It will helpful for beginners to create deocder using this.testbench for simulation is also created.
Multiplieur-signe
- VHDL code of a signed mixer with a testbench !
74serie-code
- 74系列的源代码 里面还包含了testbench和详细的代码说明-Prepared by flash controller vhdL source code. Contains testbench. Programming Language:VHDL, Tags:VHDL-FPGA-Verilog,
8051_latest.tar
- 8051 Rev 0.2 OpenCores VHDL core with testbench
serialdivider-model
- this is serial divider model vhdl file and testbench not included
pci_code
- PCI接口程序，采用VHDL语言，包括主程序和testbench文件-PCI INTERFACE IN VHDL
spi_master
- 用VHDL编写的一个SPI主机程序，SPI模块采用最常用的模式0方式（即CPOL=0,CPHA=0）通信。文件内含测试文档，已在Modelsim6.5上测试通过，可在FPGA上直接调用。-A SPI Master code edited by VHDL language,the SPI modul use 0 MODE(i.e CPOL=0,CPHA=0)to communicate with the SPI Slave.and there is a testbench in the file
vhld_tb_latest.tar
- 一个VHDL的测试平台，可以用来验证MircroProcessor，有完备的文档和代码。-A testbench based on VHDL language, you can apply it to verify a simple mircroprocessor, include complete ducoment and sources
pplllrarl
- 用VHDL写的数字锁相环程序源码 pll.vhd为源文文件 pllTB.vhd为testbench 可直接使用。 -Written using VHDL digital PLL pll.vhd program source code for the source text file pllTB.vhd testbench can be used directly.
six-digit-counter-with-tb
- VHDL source code of six digit counter with testbench,with comments included
2-to-4-Decoder-with--Configuration
- 2-to-4 Decoder with Testbench and Configuration This set of design units illustrates several features of the VHDL language including: Using generics to pass time delay values to design entities. Design hierarchy using instantiated components.
Full-Adder
- 用VHDL实现的全加器，采用dataflow style编写，是学习VHDL入门级的好范例. 包括主程序和测试程序-Full adder by using VHDL, dataflow style writing. It is a good example of VHDL especially for the entry-level leaner（Testbench included）
counter2b
- 基于vhdl完成4位计数器功能的实现，并基于此程序完成16位加法器程序的编写，内附testbench,测试成功。-Based on the vhdl completed four counter function to achieve, and the completion of a 16-bit adder program written based on this program, enclosing testbench, the test is successful.
mux-top-module
- Vhdl implementation of Mux module using and gate or gate and with testbench
lab5_
- 这是在vhdl开发环境下模拟D-FLI FLOP,T-FLIP FLOP 和 JK-flip flop。其中包含testbench 源码。-This is the vhdl development environment simulation D-FLI FLOP, T-FLIP FLOP and JK-flip flop. Which contains the testbench source.