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Oscilloscope
- The design is designed partly in VHDL, partly in schematic drawings and targets a Xilinx Spartan-2E FPGA. However, since the design was tailored specifically for the aforementioned boards it is highly unlikely that it can be ported to other hardware.
ADPCMEncoder
- ADPCM encoder with ICON, VIO, ILA, working on Xilinx ISE and chipscope.
ADPCMDecoder
- ADPCM decoder working on Xilinx ISE 12.2 code includes core ICON ILA VIO test on chipscope
perjoko_ting_ting
- Simple Microprocessor built with XILINX ISE
main1
- vhdl code for vga port interfacing of spartan 3 (xilinx) displaying colour pattern
A_digital_WaveformGenerator_and_Oscilloscope_based
- 一种基于BASYS开发板(Xilinx Spartan-3E FPGA)的波形发生器和示波器的设计，可以产生多种可调波形，并实时显示在电脑显示器或者投影仪上。波形发生器采用基于ROM的数字控制振荡器（NCO）实现，示波器采用VGA接口实时显示。-A kind of digital WaveGenerator and Oscilloscope based on tne BASYS experiment board which has a Xilinx Spartan-3E FPGA on it.T
XILINX_Spartan_3_Snake_Project-VHDL_Code
- A snake game implemented on the XILINX SPARTAN 3 FPGA board. In addition, various simple songs can be played in background, selected with the swithes.
Xilinx_PCIE_DMA
- Xilinx芯片所有关于PCI Express接口的DMA源代码，包含相关的配套的文档资料。-Xilinx chip on the PCI Express interface for all DMA source code, including relevant supporting documentation.
virtex5
- Virtex® -5 devices are configured by loading application-specific configuration data—the bitstream—into internal memory. Because Xilinx FPGA configuration memory is volatile, it must be configured each time it is powered-up. The bitstream is l
alu32
- 32 bit ALU design using VHDL code for Xilinx ISE Foundation
SpiMaster
- This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an
ThetrainingcourseofXilinxcompany
- xilinx公司2007年上海培训课程资料，主要是PPT。非常好的资料-xilinx Shanghai in 2007 training material, mainly PPT. Very good information
Xilinx-labs-manual
- a Xilinx lab manual which contains sample codes and programming techniques which are used by beginners to learn VHDL
carry-ripple
- carry ripple adder code (whole project) in vhdl using xilinx tool. VHD file has source code
xilinx
- it contils more vhdl codings and is very useful
finial_test
- 卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
spi_int
- realize spi interface vhdl code xilinx help ths help developers
xapp1022
- xilinx FPGA利用MET平台测试PCIe IP核的说明文档与源文件、-xilinx FPGA platform testing by MET PCIe IP core documentation and source files
IVK_DVI_DVI_Pass_Through_Demo
- Xilinx IVK demoboard 上DVI to DVI 範例程式源碼-Xilinx IVK example programs on the DVI to DVI pass through demo code
UART
- 串口VHDL程序，Xilinxṩ 测试成功。-Serial VHDL program, Xilinxṩ test was successful.