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曼彻斯特编解码 Xilinx提供_vhdl
- 曼彻斯特编解码 Xilinx提供的VHDL的源代码-Manchester codec Xilinx provide VHDL source code
USB控制器VHDL程序
- USB控制器VHDL程（usb_xilinx_vhdl）,用XILINX公司的FPGA实现-VHDL-USB controller (usb_xilinx_vhdl) XILINX FPGA
Wiley.FPGA.Prototyping.by.VHDL.Examples.Xilinx.Sp
- Wiley,FPGA Prototyping by VHDL examples Spartan 3 version,Pong Chu,
s3ask_ddr2
- DDR2-400样例源代码，用于Xilinx Spartan 3A/3AN Starter Kit-DDR2-400 sample source code for Xilinx Spartan 3A/3AN Starter Kit
Bch15_5
- The attached file consists of implimentation of BCH codes in VHDL programming using XILINX software. This code will reduce the no. of gates requirement.
afifo_0916
- 异步FIFO，使用XILINX产品实现，可以通过改参数来重新修改深度和位宽-Asynchronous FIFO, using the XILINX product realization, you can change parameters to re-modify the depth and Width
SDRAMController
- xilinx公司SDRAM的参考设计,调试成功-xilinx' s SDRAM reference design, debug successful
liushuideng
- 基于XILINX公司FPGA的流水灯代码，采用硬件描述语言VHDL-XILINX' s FPGA-based water lamp code, using hardware descr iption language VHDL
usb_fpga_1_2_latest.tar
- USB2.0的FPGA内核，使其可以通过FPGA控制CY公司出品的CY7C68013USB微控制器，对USB设备进行读写操作。-• Xilinx Spartan-3 XC3S400 FPGA • High-Speed (480 MBit/s) USB interface via Mini-USB connector (B-type) • Cypress CY7C68013A/14A EZ-USB-Microcontroller • 60 G
VHDL
- VHDL语言很严谨，通过对他的学习，编程思维更严谨！这个是很好的VHDL的总结内容，很好对于初学者！-VHDL language is very precise, through his learning, programming, more rigorous thinking! This is a good summary of the contents of VHDL, very good for beginners!
mdf-code-xilinx
- median filter code in VHDl
RGB-YUV
- VHDL xilinx RGB2YUV for LEARN
Demo-Design-for-Kit-Board
- 基于XIlinx FPGA 开发板的一些经典参考设计-Demo Design for the Starter Kit Board of Xilinx FPGA
Xilinx-ISE-10.1-Quick-Start-Tutorial
- VHDL Xilinx ISE 10.1 Quick Start Tutorial
Half-Adder
- xilinx ISE平台提供1位半加法器，模块随模拟提供(Half- adder 1- bit design implemented in ISE XIlinx Design Suite. Module in VHDL language)
VHDL-FIR-filters
- ynthesizable FIR filters in VHDL with a focus on optimal mapping to Xilinx DSP slices. This repository contains a transposed direct form, systolic form for single-rate FIR filters and a custom parallel polyphase FIR decimating filter. The VHDL has be
3-8译码器VHDL描述
- 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4；利用XIlinX编程，使用VHDL语言来描述组合逻辑器件3-8译码器(In the FPGA:Spartan-3E development board series, XC3S500E, FGT320, -4 package: speed; the use of XIlinX programming, using VHDL language to describe the combination
可逆计数器VHDL描述
- 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4，利用Xilinx ISE软件，利用VHDL软件编写可逆计数器，包含实验说明以及代码实现VHDL.doc文件,UCF管脚绑定文件(In the FPGA:Spartan-3E development board series, XC3S500E, package: FGT320, speed -4, using Xilinx ISE software, written in a reversible
按键去抖电路VHDL描述
- 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4，利用Xilinx ISE软件，利用VHDL软件编写按键去抖电路，包含实验说明以及代码实现VHDL.doc文件,UCF管脚绑定文件(In the FPGA:Spartan-3E development board series, XC3S500E, package: FGT320, speed -4, using Xilinx ISE software, write the debounce cir
4_pll_test
- 基于Xilinx的Artix7实现PLL。(Implementation of PLL based on Artix7)