搜索资源列表
01.ISE8.2
- 这个是我用的合众达试验箱里面的资料。合众达试验箱里面集成的是xilinx的virtex4,这个是在ise环境中审计的程序,包括led,da/ad转换实验,键盘实验,以及rtc读取和lcd显示等。-vhdl programs that used by xilinx virtex4
vga_game_demo
- 乒乓球游戏,基于Xilinx板子,并且有vga IP核,使用EDK进行编程-Table Tennis Games
xapp283
- YUV到RGB的色彩空间转换器(VHDL,Verilog and doc)-Color Space Converter: Y’CrCb to R’G’B’
AD9512_VHDL
- FPGA通过SPI总线控制Analog公司的射频时钟分配芯片的程序,在需要用到高速时钟(GHz)的电路中经常采用,比如数据采集卡及信号回放卡中会经常用到该功能,已经在产品中得到验证,工作稳定。-The VHDL code of controlling AD9512 of Analog Device
Chapter
- xilinx公司的FPGA实现数字视频信号处理器。语言是VHDL。-Xilinx FPGA to achieve the company
aa
- xilinx环境下开发vhdl语言串行接口设计-Xilinx VHDL language development environment serial interface design
spartan3elab5
- 关于xilinx大学计划配需教程实验五源代码-Xilinx University plans with regard to the need tutorial experimental five-source code
fifoi
- 基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码,深度可控-Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable
ECCgenAndLoc
- 基于xilinx ISE环境开发的VHDL的NAND flash ECC 实现,eccGen256Byte 文件夹为ECC 产生程序,EccErrLoc文件夹为ECC错误定位程序。-Xilinx ISE environment based on the development of VHDL the NAND flash ECC to achieve, eccGen256Byte folder produced for the ECC procedures, EccErrLoc folder l
uart
- 串口通讯rs232,时钟频率为40Mhz,波特率为19200,没有奇偶校验,在xilinx XC3S200A板子上验证过.-Serial communication rs232, clock frequency of 40Mhz, the baud rate to 19200, no parity, in the board on xilinx XC3S200A verified.
clock_module_ref
- Xilinx clock module design
pro104_uart
- uart的代码,经实际运行可以通信,是xilinx uart 代码的改进,网上的xilinx uart代码有很多bug,用此代码可以改进运行。-UART code, the actual operation can be communication, xilinx uart code are improved, xilinx uart code online has a lot of bug, the code can be improved with this operation.
11_vga
- This vga controller write in vhdl xilinx ise Connect your vga monitor and view many color in moniotr-This is vga controller write in vhdl xilinx ise Connect your vga monitor and view many color in moniotr
lab5
- VHDL xilinx例子-vhdl xilinx example............
BUFG_CLK2X_FB_SUBM
- xilinx DCM 应用的源代码,完全可用-xilinx DCM application source code, fully available
Simulation-and-FPGA-Implementation-of-DigitalDBPSK
- 文章介绍了系统的硬件电路原理与具体实现方法,其中主要包括载波恢 复电路,PN 码捕获电路和跟踪电路,并针对Xilinx 公司FPGA 的特点,对各电 路的实现进行优化设计,在不影响系统稳定性和精度的前提下,减少硬件资源 消耗,提高硬件利用率。设计利用Verilog 硬件描述语言完成,通过后仿真验证 电路正确性,并给出综合结果。-This paper introduces the system' s hardware circuit principle and the spe
fifo_core
- 经典的FIFO实现源码,里面有三种类型,是xilinx工程师写的,经典-Classic source FIFO implementation, there are three types, are written by xilinx Engineer, classical
READ
- 用于FPGA实现单总线测温电阻DS18b20时序。在xilinx spartan 3中试过。-failed to translate
guard_against_theft
- 利用XC9572-PQ44(Xilinx CPLD)制作的一款家用防盗报警器的Verilog源代码及原理图,当房门打开后,15秒内若没有按下Key1,则会自动拨打设定手机号(当然,要另连接一台手机)-Using XC9572-PQ44 (Xilinx CPLD) produced by a home burglar alarm of the Verilog source code and the schematic diagram, when the door opened, within 15
kp_lcd
- This is Keypad and LCD interface C code Tested on Sparton 3 xilinx FPGA.