搜索资源列表
sfifo_srl
- 针对XILINX FPGA特有的SRLC16E器件，实现的同期FIFO. 特点：宽度深度可配置，面积小。-SRLC16E Based Synthesise FIFO Implement by Xilinx FPGA. The Size is small and FIFO Width, Length can be configured.
arithmetic
- 这是xilinx的FPGA实现各种算数运算的全部基于MATLAB的模型文件，包括加减乘除等-This is the xilinx arithmetic FPGA to achieve the full range of MATLAB-based model of documents, including multiplication and division, such as addition and subtraction
Exp1-Led
- 本次实验使用 Xilinx FPGA的开发工具 ISE6.x，新建一个工程，并进行综合、布局布线、 下载配置。 这里建立的工程是使用 Create-SOPCMB上的发光二极管显示一个八位二进制计数器， 发光二极管亮表示该位为 0。 -Experimental use of the Xilinx FPGA development tools ISE6.x, create a new project, and comprehensive, the layout of wiring, d
stopwatch
- The program is written in verilog to accomplish functions of a stopwatch. It can be implemented in Xilinx FPGA spartan 3 board.
amp
- 本资料主要是Xilinx对于DDR2的IP核的一个简单应用-This information is Xilinx' s IP for DDR2 a simple application of nuclear
ISE
- 介绍Xilinx公司FPGA/CPLD的集成开发环境——ISE软件的简单使用，该软件环境集成了FPGA的整个开发过程所用到的工具。主要介绍了用VHDL、VerilogHDL、原理图以及用ModelSim 仿真工具对设计进行功能仿真和时序仿真以及将数据流文件加载到FPGA等方面的内容。-Xilinx Inc. introduced FPGA/CPLD integrated development environment- ISE software simple to use, the softwa
50TDDD
- 这是XILINX公司V5-665-1的例程，我试过了 好用，大家可以试试！！~-This is the XILINX' s V5-665-1 of the routines, I tried the easy to use, we can try! ! ~
Vme_Interface
- 这是本人设计的一个关于VME总线接口的FGPA程序，FPGA一边连接ARM LPC2294，一边连接VME总线，FPGA采用的XILINX公司的SPARTANII系列，程序包包含完整的工程文件-This is my design of a VME bus interface on the FGPA procedures, FPGA side of the connection ARM LPC2294, while connecting VME bus, FPGA using the XILINX
ml507_ibert_4gtxs
- xilinx 公司的有关power_pc 的资料，是xilinx公司的源代码。-xilinx a relevant power_pc information is xilinx the company' s source code.
c_xapp851
- 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM （JEDEC DDR400 (PC3200) 标准）控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes
Leds
- Multiple frequency dividers in VHDL, with comments in Spanish. Is a project done with Xilinx ISE application. It divides 50 MHz in 1, 2, 4 and 8 Hz.
This_is_pci-wishbone_nuclear_and_16450_serial_port
- 这是用pci-wishbone核和16450串口核在xilinx的FPGA上实现的。-This is pci-wishbone nuclear and 16450 serial port on the nucleus in xilinx FPGA-implemented.
video_capture_rev_1_1
- 视频图像的捕捉系统的实现，主要是基于XILINX系统的实现-Video image capture system implementation is mainly based on XILINX System
picieee.tar
- The Synthetic PIC is a synthesizable VHDL descr iption of the basic Microchip PIC 16C5X microcontroller. It is written in the ViewLogic VHDL environment (Workview PLUS 5.2). It has successfully been synthesized to the XC4000 family, although
traffic_light
- this project is traffic lights on fpga. ı used xilinx ise and simulated modelsim. [used spartan 3e development kit]. -this project is traffic lights on fpga. ı used xilinx ise and simulated modelsim. [used spartan 3e development kit].
ispdown
- 能够支持多种芯片下载，如：at89单片机，arm单片机，xilinx等芯片的下载。共能强大-Able to support a variety of chip download, such as: at89 microcontroller, arm microcontroller, xilinx chips and other downloads. A total is strong! !
high_speed_data_recovery
- 1. 程序的功能是:高速串行数据的恢复. 2. 其基本原理是：利用过采样，检测串行数据的边沿跳变，然后根据边沿提取处在数据相位正中央相邻的抽样值，将串行数据恢复过来。 3. 此程序是verilog 语言编写，用于xilinx virtexE 系列的FPGA-1. Program functions are: high-speed serial data recovery. 2. The basic principle is: the use of over-sampling to det
Rocket
- 很好的高速口的设计资料，很好的高速口的设计资料 很好的高速口的设计资料-In design of large-scale access convergence router(hereafter referred to ACR) forwarding engine, the Xilinx Virtex-4 FPGA!s RocketI/O r multi-gigabit transceiver is used to satisfy the need of high speed and st
CSC_XAPP931_pdf
- This document is Xilinx`s Color Space Conversion Applcation Note. This CSC is a RGB to YCrCb Conversion.
register
- this a project that makes a shift register using VHDL and the Xilinx platform. -this is a project that makes a shift register using VHDL and the Xilinx platform.