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1.6运算器部件实验：乘法器
- 这个是用vhdl编写的乘法器,仅仅供大家参考-VHDL prepared by the multiplier, just for reference
statemachine_mult
- veilog实现的状态机乘法器.可以参考-veilog achieve the state machine multiplier. Can reference
mutli20
- 一个乘法器的程序,经过调试的,非常好用的,去看看.-a multiplier procedures are followed, debugging and very useful, and see.
xapp195
- signed_mult乘法器通常用于DSP设计。但由于赛灵思的FPGA架构中包含有-signed_mult multiplier is used DSP design. But Xilinx FPGA architecture contains
verilog恒系数乘法器
- verilog恒系数乘法器
multiper
- 用xilinx写的vhdl乘法器。是二进制的两位乘法器。里面含有代码和电路图。-Written in VHDL using Xilinx multiplier. Binary multiplier is two. Which contains code and circuit diagrams.
hierarch_unit.tar
- 该代码是布斯乘法器代码，用于了解布斯算法，本人也是初学者。-err
Mult
- 用impulse c编写的18x18位的乘法器。-Impulse c prepared with 18x18-bit multiplier.
mul
- 加法器树乘法器结合了移位相加乘法器和查找表乘法器的优点。它使用的加法器数目等于操作数位数减 1 ，加法器精度为操作数位数的2倍，需要的与门数等于操作数的平方。 因此 8 位乘法器需要7个15位加法器和64个与门-Adder tree multiplier multiplier combination of shift and add multiplier advantage of look-up table. It uses the adder operand is equivalent to
16bit_multiply
- 一个16位并行乘法器， 已经进过功能验证， 可以用于综合。 -a 16bit parallel multiply after verification, can be used to synthesis
multi
- 8位乘法器，Quters编译环境VHDL代码-pluter VHDL Quters
Lab4
- 实现原码一位乘法器，但必须位数相同才行。-hdbadbkwdk
maths
- multiplux,8*8的单片机乘法器-for the microcontroller
multiplier8x8
- 8位定点乘法器，支持有符号数/无符号数运算。采用4-2压缩树结构，并提供testbench。-It is an 8-bit fixed-point multiplier, supporting signed/unsigned operations. Wallance tree structure with 4-2 compression. Provides testbench.
4_bit_mul
- 四位乘法器,可以实现两个四位二进制数的乘法。-4_bit_mul
Multiplier
- fpga门电路实现的8位乘法器, verilog 语言编写，ise平台(implementation of multipler)
mux16
- 用verilog写的乘法器，在quartus里可以直接运行，有详细注释(Multiplier written in Verilog, in quartus can run directly, with detailed notes)
基于FPGA的单精度浮点数乘法器设计
- 《基于FPGA的单精度浮点数乘法器设计》详细介绍了按照IEEE754标准在FPGA上实现单精度浮点加减乘除的方法(The design of single precision floating point multiplier based on FPGA introduces in detail the way of realizing single precision floating point addition, subtraction and multiplication and div
流水线乘法累加器设计
- 调用寄存器LPM,流水线加法器LPM,流水线乘法器LPM等模块实现一个8位流水线乘法累加器。(Call a register LPM, pipelined adder LPM, pipeline multiplier LPM and other modules to achieve a 8 bit pipelined multiplication accumulator.)
fpmul
- Verilog语言编写的单精度浮点数乘法器(The Verilog language of single precision floating point multiplie)