搜索资源列表
Digital_system_design_example
- 数字系统设计实例.pdf,VHDL语言实现，7.1 半整数分频器的设计7.2 音乐发生器7.3 2FSK/2PSK信号产生器7.4 实用多功能电子表7.5 交通灯控制器 7.6 数字频率计.值得一看。-digital system design examples. Pdf, VHDL, 7.1-integer divider design Music Generator 7.2 7.3 2FSK/2PSK Signal Generator 7.4 Practical multi-functi
52_divider
- 分频器，用VHDL语言编码，可能对你用处不是很大，但做为参考还是很大用处的-dividers, VHDL coding, you may not have much use, but as a reference or very useful
any_frequency_VHDL
- 任意整数分频器的vhdl源程序,放心使用. 无版权问题,欢迎copy.
fpq
- ISP实验分频器源程序，用VHDL写的，在x3s200an芯片上编译的-ISP prescaler source experiment, using VHDL written in compiled x3s200an chip
time_div
- IP 分频器 可以通过输入参数而自动调整分频数-IP divider input parameters can be automatically adjusted at the frequency
DVF
- 数控分频器的设计数控分频器 端口定义： CLK：时钟输入 D[7..0]：预置数据 Fout：分频输出 说明： D[7..0]作为8位加1计数器的初值，初值越大，分频输出频率越高，反之越低， -NC NC divider divider port the definition of design: CLK: Clock input D [7 .. 0]: preset data Fout: frequency output that: D [7 .. 0] as
divideclk
- 一个简单的由vhdl代码描述的分频器模型-it is code writing by vhdl,and it is used for divede clk
music_disply
- 音乐播放器 中的数控分频器 后续还需要添加一个分频的电路-Music player in the follow-up of NC divider also need to add a sub-frequency circuit
Crossover
- 分频器的设计，包含普通分频器和占空比为50 的奇数分频 ；4位乘法器的VHDL程序；-Crossover design, including general divider and the duty cycle of 50 of the odd frequency 4-bit multiplier VHDL procedures
div63
- 可以对增量式编码器输出的AB相信号进行整数分频。有一个简单的通讯接口，可设定分频大小。 -Incremental encoder can output an integer number for AB believe frequency. There is a simple communication interface, can set the size frequency.
shiyanliu
- 用VHDL编程实现乐曲播放器设计。使用层次化设计方法，实现乐曲播放器的设计； 使用数控分频器设计硬件乐曲演奏电路，实现多首乐曲播放功能。 -The music player design with VHDL programming. Using the hierarchical design method, design music player NC crossover design hardware music playing the circuit, the song pla
yibutongxun
- 用VHDL实现的异步通讯模拟程序和报告。分为控制器，接收器，发射器三部分，其中应用到了异步串行通讯控制器的设计以及非整数分频器的设计。-Asynchronous communication using VHDL simulation procedures and reporting. Divided into the controller, receiver, transmitter three parts, which applied to the design of asynchronous
fenpin
- 用VHDL写的一段很小的任意整数分频器，可以设置任意整数数值，来获得所要的分频值-Use VHDL to write for some small arbitrary integer divider can be set to any integer value, so as to obtain the desired divider value
vhdl--of--traffic-light
- 十字路口的交通灯vhdl控制程序，其中包括分频器、交通灯控制器和主程序三部分。-Crossroads of traffic lights the vhdl control procedures, including the three parts of the divider, traffic light controller and main program.
2.5fenpin
- 利用VHDL语言描述的5分频器（改变程序中m1,m2值，可作为任意奇数分频器-The use of VHDL language is described in 5 prescaler (change procedure m1, m2 value, can be used as arbitrary odd prescaler
Digital-clock-design
- 数字钟设计 用VHDL实现一个50MHZ到1HZ的分频器，利用Quartus II进行文本编辑输入和仿真硬件测试。实现一个60进制和24进制的计数器。测试成功。-Digital clock design using VHDL a 50MHZ to 1HZ divider using Quartus II simulation for text input and editing hardware test. Achieve a 60 hex and 24 hex counter. Test wa
fenpinqi
- 基于vhdl语言编写的分频器程序，可实现五十分频。-Based divider vhdl language program, can achieve five very frequently.
分频显示
- VHDL实验中，实现分频与数码管显示。掌握BCD-七段显示译码器的功能和设计方法； 掌握用硬件描述语言的方法设计组合逻辑电路——BCD-七段显示译码器。(In the VHDL experiment, frequency division and digital tube display are realized.)
plj
- 使用vhdl语言原件例化设计数字频率计，并用6位7段数码管计数。模块包括：十进制计数器，6位10进制计数器，Reg24 锁存器、Fp 分频器、Ctrl 频率控制器、Disp 动态显示。(The digital frequency meter is designed by using VHDL language as an example and counted by 6-bit 7-segment digital tube. Modules include: decimal counter, 6