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一种基于FPGA的并行流水线FIR滤波器结构
- 这是我看到的一些资料，希望与大家分享。也许这对您用处不大，但是我的一份诚意。-this is that I see some of the information and hope to share with you all. This may be less useful to you, but my sincerity.
利用Java实现串口全双工通讯
- 一个嵌入式系统通常需要通过串口与其主控系统进行全双工通讯，譬如一个流水线控制系统需要不断的接受从主控系统发送来的查询和控制信息，并将执行结果或查询结果发送回主控系统。本文介绍了一个简单的通过串口实现全双工通讯的Java类库，该类库大大的简化了对串口进行操作的过程-an embedded system usually through its serial port control system for full-duplex communications, For example, a pipe
statemachine11.2
- 推荐下载,verilog状态机实例.体现了流水线思想的应用 -recommend downloading Verilog state machine example. Pipeline reflects the thinking of the application
udptransport
- 基于UDP实现简单的可靠数据传输 由于数据是在不可靠的信道上传输的，因此数据在信道上传输时可能会发生比特错误，数据丢失。Rdt3.0及之前的版本都是停止—等待协议，它限制了网络底层硬件的能力。为克服这个问题引入了流水线技术，两个能恢复流水线中的错误的基本方法：第N个分组重发和选择性重复。综上，要实现差错编码，顺序号，计时器，分组确认，滑动窗口，拥塞控制。-simple UDP based on the reliable data transmission of data is not rel
MutiplierDesign
- 流水线乘法器,vhdl语言描述, 希望对大家有所帮助 -pipelined multipliers, vhdl language, we hope to help
WinDLXcourseDesign
- WinDLX的实验,除了代码优化的部分全部完成,包括流水线的分析.-WinDLX experiments, in addition to the optimization of code completion, including pipeline analysis.
PipeLineNewVisual
- CPU内部流水线过程模拟程序，对其中各种状态进行模拟，并给出实时状态
三维流水线
- 三维流水线的功能-functional 3D Pipeline
MIPS五级流水线模拟程序
- MIPS五级流水线模拟程序，能执行简单的MIPS指令，模拟流水线状态及寄存器结果，实现cpu流水的概念-MIPS five-level stream-line simulation program, this program can execute simple MIPS instruction, simulat stream-line s status and register result, and it implements stream-line of cpu.
pipeline
- 计算机原理大作业 模拟《计算机原理--程序员视角》中与x86相似的y86流水线系统 以二进制文件为输入 实现流水线运作-Principle of operation of computer simulation of large computer Principle- Programmer Perspective in y86 and x86 assembly line system similar to the binary file for input to achieve the op
liushuixian
- 功过模拟单功能流水线调度过程，掌握流水线技术，学会就算流水线的吞吐率，加速比，效率-Merits and demerits of single-function simulation pipeline for the activation process, master pipeline technology, even if the pipeline throughput Institute, speedup, efficiency
pipeline
- 有关流水线的功能的西安交大的课件,讲的很详细，很好-about pipeline in pdf text
cpu16
- 实现一个16位CPU。该CPU使用精减指令集，是一个五段流水线的结构。包括取指令(IF)、读寄存器(RD)、运算器(ALU)、内存读写(MEM)和写回(WB)。-The realization of a 16-bit CPU. Streamline the use of the CPU instruction set is a structure of five lines. Including fetch (IF), register read (RD), arithmetic logic u
6_seg_cpu
- 我写的6段流水线cpu，供大家参考。里面包括了alu memory topcpu等模块-I wrote a six-stage pipeline CPU, for your reference
WinDLX
- DLX模拟器用软件模拟DLX流水线的工作过程，可以灵活、方便地设置参数、控制执行和统计数据，并提供了直观的窗口显示。-DLX simulator software simulation of DLX pipeline work process can be flexible and easy to set up parameters, control, execution and statistical data, and provides an intuitive window display
80870991pipeline
- 计算机体系结构中关于通用5级流水线的模拟实现程序-Computer architecture in general 5-stage pipeline on the implementation process simulation
flow
- 五级流水线模拟，使用C++模拟，取指、译码、执行、访存和写会-five step flow
.net商品(农产品)完整流水线追溯系统源码
- .net商品(农产品)完整流水线追溯系统源码 网络搜集整理 希望对大家有所帮助(.net commodity (agricultural products) complete pipeline tracing system source code Network collation hopes to help people)
无线传输程序417
- 流水线产品检测上位机程序，上位机程序，用VB进行编写(PC program, written in VB)
流水线乘法累加器设计
- 调用寄存器LPM,流水线加法器LPM,流水线乘法器LPM等模块实现一个8位流水线乘法累加器。(Call a register LPM, pipelined adder LPM, pipeline multiplier LPM and other modules to achieve a 8 bit pipelined multiplication accumulator.)