搜索资源列表
DE2_LCD
- 本源码是用verilog编写控制LCD——使用Quartusii，开发平台使用的是DE2开发板，可实现1602上任意字符显示
DE2_i2sound
- 这是一个基于DE2平台的工程，适合于初学者学习DE2开发平台的很好的工程，是用Verilog语言编写的
UnsignMulti
- ALTERA上DE2平台，verilog描述，无符号乘法器，在数码管显示结果。
hex_7seg.rar
- altera DE2开发板上数码管译码的verilog程序,altera DE2 development board Verilog digital tube decoding procedures
pingpong
- 在DE2开发板上实现的一个简单乒乓球的程序。开发语言verilog-In the DE2 development board to achieve a simple ping-pong process. Development language verilog
VDE22_NIOS_HOe
- Verilog代码，适合于初学入门者者进行学习，是一种基于DE2平台的代码。 -Verilog code, suitable for novice beginners to learn, a code based on the DE2 board.
VGA_Controller
- 由Verilog HDL编写的VGA控制器模块，可用于DE2板子。-For DE2 board VGA controller module written in Verilog HDL.
DE2_Default
- DE2开发板 verilog语言描述 Quartus II环境-DE2 development board verilog language to describe
miaobiao
- 这是用verilog写的一个关于秒表实现的程序，已在DE2上成功实现-Verilog write a stopwatch to achieve the program has been successful on the DE2
Timer
- 用verilog语言实现的定时器。在DE2-70开发板上设计，七段数码管分别用于显示时/分/秒，并带有预置时间功能。-Timer verilog language. DE2-70 development board design, seven-segment digital tubes were used to display hours/minutes/seconds, with the function of the preset time.
DE2-70
- DE2-70 FPGA开发板学习实例及代码，Verilog HDL-DE2-70 FPGA development board learning examples and code, Verilog HDL
Counter_10
- verilog 计数器，每计数到十清零，可以直接下载到DE2-70开发板-verilog counter
project1
- 4比1多路选择器，HDl verilog语言编写，能在DE2上运行-4 to 1 multiplexer, HDl verilog language, able to run on the DE2
pinpongf16
- FPGA Verilog程序 采用DE2-70 Altrer 实验班实现小球跳动-FPGA Verilog program using DE2-70 Altrer experimental class of small ball beating
jiaozhi
- 完成通信系统中数据交织器的设计的设计，要求用Verilog HDL编程，在DE2平台上实现，在示波器上显示观察。-Complete data communication system Interleaver Design for the design, requirements using Verilog HDL programming, implemented on the DE2 platform, observed on the oscilloscope display.
paobiao
- verilog实现数码跑表，基于ALTERA DE2—70开发板实现验证，其中代码不分模块。-verilog achieve digital stopwatch, to achieve certification based ALTERA DE2-70 development board, regardless of where the code module.
DE2_70_SD_Card_Audio_Player
- DE2-70 SD card player verilog and nios ii code
fdfd
- 第二章 设计思路 2.1 设计总体框图 有分析可知，本次课程设计可以分成五个木块来实现相应的功能，分别是输入模块，计算模块，扫描模块，输出模块以及显示模块。((Calculator design based on FPGA DE2 development board. language use Verilog. Matrix keyboard input, LCD1602 display. Program includes key scanning module and LCD modul