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uart_rx
- Tcode is in VERILOG HDL (Hardware descr iption language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL
5_bluetooth_uart
- 基于FPGA，硬件平台：basys3，软件平台：vivado。描述语言：verilog。封装自己的蓝牙串口IP。蓝牙串口数据传输需要三个模块，分别是波特率生成模块，接收模块和发送模块。-Based on the FPGA hardware platform, software platform: basys3, vivado. Descr iption: verilog. Package your own Bluetooth serial port IP. Bluetooth serial da
vhdl
- 利用vhdl语言实现（7,4）汉明码编码过程，在FPGA上实现，并且通过串口发送个计算机，在计算机上显示。-Use vhdl language (7,4) Hamming code encoding process, implemented on the FPGA, and send a computer through the serial port, the display on the computer.
SCH
- DTMB GB20600-2006 terrestrial dig FPGA or CPLD reads the SD card IP tell us how to divide frequency f UMC 90nm design models. please re UMMC 90nm models. Please read the Bluetooth serial port via the pho scope FPGA code AG 0.35u
Receiver
- FPGA SPI串行收发数据全双工程序开发，使用Verilog HDL开发语言-FPGA SPI serial port to send and receive data all double engineering sequence development, using Verilog HDL language development
kehshechenxu
- 编制一全双工UART电路，通过试验箱MAX202E转换成RS232电平，与计算机进行通讯实验，设置8个按键，按键值为ASIC码“1”~“8”，通过串口发送给计算机，在计算机上显示键值，同时在数码管最高位显示；计算机可发送“0”~“F”的ASIC码，FPGA接收后在数码管低位显示0~F。通过按键可设置波特率。 要求：波特率为三种 1200、2400、9600，由1个按键选择，3个LED分别指示； 数据格式为1位起始位、8位数据位和一位停止位； 上位计算机发送接收软件可使用
uart_2_pc
- 实现FPGA和PC通过串口传输数据，已经通过验证，可以结合自己的设计直接拿来用(ealize FPGA and PC to transmit data through serial port)
蓝牙控制bluetooth
- FPGA蓝牙无线控制LED，蓝牙驱动，已验证通过，手机蓝牙串口直接发送(FPGA Bluetooth wireless control, LED, Bluetooth driver, has been verified through the mobile phone Bluetooth serial port to send directly)
counter_frequency - 副本
- FPGA制作频率计并且通过串口连接并进行显示(FPGA drive frequency meter and display with serial port)
FPAG UART Verilog
- FPGA实现URAT，实现异步串口收发控制(FPGA implements URAT to realize asynchronous serial port and transceiver control)
基于FPGA与PC串口自收发通信-Verilog
- 基于FPGA与PC串口自收发通信-Verilog(Self-transceiving Communication Based on FPGA and PC Serial Port-Verilog)