This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave

SPI slave source code

simple spi slave operating in mode 0 in VHDL.

利用VHDL在FPGA内实现SPI总线的主从控制器设计(SPI Master and Slave Controller)