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1.7运算器部件实验:除法器
- 这个是用vhdl语言编写的除法器,仅仅供大家参考.-the VHDL language is used to prepare for the division, just for reference.
fpga_div
- Altera的FPGA,设计的硬件除法器-Altera' s FPGA, the design of the hardware divider
restoring
- restoring除法器设计 经典算法了,可以仿真通过-divider restoring a classical algorithm design, simulation can be adopted
4_bit_division
- 4位除法器,文件内容为QUARTUS II支持的VHDL语言,用于做四位除法-4_bit_division
diver
- 利用VHDL语言设计了五位除法器 实验环境为maxplusII 内有各个模块详细的程序代码 以及相应的模块截图-Designed using VHDL, five divider within the experimental environment maxplusII detailed code of each module and the corresponding module screenshot
div
- vhdl除法器 vhdl除法器 vhdl除法器 -divider vhdl vhdl vhdl divider divider divider vhdl vhdl vhdl divider divider
float-point-divider
- 基于FPGA的单精度浮点除法器vhdl设计程序,分模块程序。-FPGA-based single-precision floating point divider vhdl design program, sub module program.