搜索资源列表
allidt_20020616.tar
- idt的双口ram的读写接口程序，verilog 代码，并且有测试文档-Employing a dual-port ram reader interface program, Verilog code, and a test document
ram
- verilog写双端口存储器模型-a Model of Writing Double-Port RAM developed with Verilog
ram_sp_sr_sw
- Synchronous read write RAM verilog
ddpi_tx
- verilog语言编写的一个接口文件，使用乒乓ram-verilog language of an interface file, use the ping-pong ram
interleaver
- This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
RAM
- 双口RAM Verilog描述 双口RAM Verilog描述-Dual-port RAM Verilog descr iption of dual-port RAM Verilog descr iption of dual-port RAM Verilog descr iption of
rom_prf_gen
- 用ram存储顺序，用此方法也可以实现其他的顺序数据，代码用verilog编写-Ram memory with the order can be achieved using this method also the order of the other data, write code using verilog
verilog_RAM
- verilog 实现的一个双口RAM及其控制模块.我通过先存入64个数据在读出仿真通过。-verilog implementation of a dual-port RAM.
try_ram
- Verilog Codes for RAM-Testing. Write data in the RAM and read it out from the RAM. Tested on NEXYS 3.
RF128x32
- 基于verilog的128*32RAM设计代码-The RAM-based design code verilog
RAM
- 通过使用fpga，verilog语言来实现RAM的读写功能。-for ram reading and writing
cpu_me
- 采用verilog编写的cpu,modelsim仿真均实现8条指令功能，有虚拟ram和rom-Using verilog prepared cpu, modelsim simulation functions are to achieve eight instructions, there are virtual ram and rom
gds8k_32bit_1M
- 一款SRAM的verilog代码及版图信息-verilog codes and layout information of a RAM
AHB RAM
- Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)