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ahb_system_generator.tar
- An AHB system is made of masters slaves and interconnections. A general approach to include all possible \"muxed\" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a mas
ahb2ahb.rar
- AMBA总线AHB TO AHB bridge,AMBA bus AHB TO AHB bridge
ahb_interface.rar
- AHB BUS, Master Slave Arbiter -- example,AHB BUS, Master Slave Arbiter
ahb_arbiter
- USB v1.1 RTL and design specification
appnote65_quickmips_ahb_interface_design_example.r
- appnote65_quickmips_ahb_interface_design_example AHB接口设计-appnote65_quickmips_ahb_interface_design_exampleAHB Interface Design
Advanced_Buses
- multi-layer ahb descr iption
ahb2pvci
- ahb to pvci bridge, free code
ahb05
- amba ahb verification documents -amba ahb verification documents ..............
AHBPAPB
- AMBA总线的AHB+APB源程序，供初学者学习。-Verilog for AHB and APB
ACODEH
- AHB总线下的slave ramm的verilog代码 -Verilog code of the AHB bus slave ramm
ahbctrl
- AMBA2.0,ahb总线控制器的实现，来自leon3开源代码-AMBA2.0, the implementation of ahb bus controller, from leon3 open source code
apb_bridge
- AMBA AHB总线上连接慢速设备的slave,通过 apb_bridge桥实现AHB到APB的转换-AMBA apb_bridge
amba_slave_to_wb.tar
- ahb slaver to wb, it s very useful for code farmer
ahb_fsm
- AMBA AHB design code.rar
AHB
- AHB_Verificaion_Code
ahb2apb-master
- ahb to apb master and slave
ahb2apb_bridge_verification-master
- ahb to apb master verification
AHB RAM
- Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
AHB
- 基于amba总线协议中的ahb总线的从机模块代码,需要modelsim进行测试仿真(Based on the slave bus module code of AHB bus in AMBA bus protocol, Modelsim is needed to carry out test simulation.)
AHB2-master
- verilog ahb master and slave