搜索资源列表
aes-verilog-imp
- AES加密算法的硬件实现，硬件语言为verilog-AES encryption algorithm hardware implementation, hardware verilog language
AES
- AES算法的verilog代码，即AES算法IP核-ip core for AES
systemcaes_latest.tar
- 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
aes_crypto_core_latest.tar
- verilog code for aes
aes_thesis_v1.0
- AES VERILOG CODE 128 192 32DES比較-AES VERILOG CODE 128 192 32DES Comparison
AES_verilog
- AES 128bit数据,128bit密钥加解密的verilog语言实现-AES 128bit data, 128bit key encryption and decryption of the verilog language implementation
aes
- 其程序是用xilinx环境下编写的，风格是Verilog，请大家提意见。-The program is written using xilinx environment, style Verilog, please comments.
aes_crypto_core_latest.tar
- AES加密算法的Verilog实现，不包括测试文件-Verilog realization of AES encryption algorithm, not including test file
aes-module
- its a aes source code in verilog
AES-based-on-FPGA-jiami
- 该模块是基于FPGA的AES加密算法实现的Verilog代码，包含一个顶层文件和两个调用模块，最高误差在15ns-This module is the AES encryption algorithm FPGA based on the Verilog code, contains a top-level files and two call module, the maximum error in 15ns
aes
- AES的IP核,AES的加密解密算法，包括密钥扩展程序-aes core verilog
AES
- AES128的verilog实现，仿真通过。-AES128 the verilog achieve, through simulation.
AES
- AES加解密Verilog HDL源代码，具体的算法参照相关书籍，里面含有testbench-AES encryption and decryption Verilog HDL source code, reference books specific algorithm, which contains testbench
FPGA-IMPLEMENTATION-OF-AN-AES-PROCESSOR
- Advanced Encryption Standard(AES) implementing in a faster and secured way is expected. AES can be implemented in software/hardware. In hardware implementation ASIC solution requires high cost and much design time while FPGA based implementation
AES
- aes源码verilog带有仿真环境，可用于FPGA实现-aes verilog rtl
aes
- 使用verilog的128位aes加密源程序-Use verilog of 128 aes encryption source code
aes_thesis_v1.0
- aes code in verilog vhdl language which is very useful.
aes
- AES in verilog codes
AES-GF(2^4)^2 for sbox
- AES加解密程序，128bit数据位宽，其中sbox和混合列运算在复合域GF(2^4)^2上完成(An AES encryption and decryption program with 128 bits datawidth, which used GF(2^4)^2 for sbox and mixcolumn.)
aes-master
- Verilog写的AES加密解密代码，带testbench。(AES encryption code written by Verilog with testbench.)