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fifo
- 一个FIFO的原代码 非常有用 给大家共享了 下吧
FX2-Slave-FIFO
- 这是基于CY7C68013芯片，工作于slave FIFO模式的数据传输的程序。包括USB固件程序的程序框架和传输功能实现程序。
serial.rar Dos 串口通信例程实现了FiFO
- Dos 串口通信例程实现了FiFO ,中断发送中断接受！,Dos serial communication routines to achieve a FiFO, interrupted send interrupt accepted!
SCI_FIFO.rar
- F2812 SCI FIFO中断发送和接收例程,F2812 SCI FIFO interrupt routines to send and receive
Verilog_CY7C68013-SLAVE-FIFO
- 用VERILOG 编写 CY7C68013 usb数据采集SLAVE FIFO模式驱动程序 ，已验证过-Prepared with the VERILOG CY7C68013 usb data acquisition SLAVE FIFO mode driver, has proven
asfifodesign
- 异步fifo设计文档，里面包括详细的verilog设计方案及代码。fifo设计是通信中必然设计的设计-a fifo design with code inside, using verilog language
bulkloop
- EZ-USB FX2 SLAVE FIFO模式固件代码-EZ-USB FX2 SLAVE FIFO mode firmware code
Apptest_write_read_fifo
- 采用EZ-USB GPD开发的USB FIFO测试程序-The use of EZ-USB GPD development of USB FIFO test procedures
Uart(FIFOSend.TimeoutReceive)
- AVR mega16/mega32的UART FIFO发送.超时接收,广泛应用于工业控制.这是原创作品.-AVR mega16/mega32 send the UART FIFO. Overtime receiver is widely used in industrial control. This is the original works.
usb
- USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control,
SCI_TXRXFIFO_over
- SCI串口通信程序，使用FIFO功能，定时收发-SCI serial communication, the use of FIFO function, periodically send and receive
async_fifo
- 异步fifo 源程序代码 欢迎大家学习 用VHDL语言编写-asy fifo
asynchronous_fifo
- Fully asynchronous fifo for Altera devices.
fifo
- 基于verilog的fifo异步实现的源代码和分析。-fifo
UART0_FIFO
- LPC2106的串口的FIFO仿真程序，使用ads编辑的。-LPC2106 emulator serial port of the FIFO, using ads to edit.
FX2-Slave-FIFO
- 最常用的USB数据采集系统 CY7C68013 SLAVE FIFO 模式 不需要修改，已验证过-The most common USB data acquisition system CY7C68013 SLAVE FIFO mode does not change, has been verified
fifo
- fifo buffer in vhdl, first in first out in vhdl, vhdl code
fifo
- fifo源码以及测试文件基于ISE14.2-fifo source and test files based on ISE14.2
Slave-FIFO
- 详细讲解Slave FIFO模式下的初始化设置和相对应寄存器说明-Explain in detail the initial setup Slave FIFO mode and the corresponding register descr iption
fifo
- Verilog HDL实现通用的FIFO的一个demo，可以参考这个程序根据自己的需求更改深度和宽度，以及标志位(Verilog HDL implements a demo of a generic FIFO that you can refer to to to change the depth and width, as well as the flag bits, depending on your needs)