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my_pll
- VHDL程序，使用锁相法实现位同步的算法，并可以对算法进行仿真-VHDL, the use of lock-in-law to achieve the synchronization algorithm, the algorithm can be simulated
I-rife
- 频率估计，是一种比较简单的算法，很基础，有助于初学者应用-Frequency estimation, is a relatively simple algorithm, it is based applications to help beginners
viter2
- verilog实现卷积码的译码，viterbi算法-verilog to achieve the decoding convolutional codes, viterbi algorithm
viterbi
- 一个vitrtbi算法的参考实现,verilog的-A reference implementation vitrtbi algorithm, verilog of
verilogHDL
- RS（31，15）译码关键步骤的veilog HDL算法实现，包括关键方程求解，错误位置估计，错误值计算等-RS (31,15) decoding a key step in the algorithm veilog HDL, including key equations, position estimation error, error value, such as
hash
- 适用于RFID安全认证协议的轻量级hash算法，输出64bit数据。-Applicable to lightweight RFID authentication protocol security hash algorithm, output 64bit data.
turbocodes_latest.tar
- 基于sova算法的Turbo码解码VHDL工程文件，非常经典，包含Python高层仿真代码。-Turbo Decoder Release 0.3 MAIN FEATURES - * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizabl