搜索资源列表
usb_doc
- USB IP core.very good
USB2.0_rtl_ipcore_verilog
- 经过门级网单验证的USB2.0 IP核 RTL代码-net after gate-level verification of USB IP Core RTL code
simple_spi
- 一个简单的ＳＰＩ ＩＰ核，SPI Core Specifications 可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchron
grlib-gpl-1.0.15-b2149.tar
- free hardware ip core about sparcv8,a soc cpu in vhdl-free hardware ip core about sparcv8. a soc cpu in vhdl
usb20_ipcore_usb_funct
- usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL descr iption suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
USBipcore
- usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
bluetooth.tar
- 蓝牙的一个ip RTL 核，不知道对大家有没有用？谢谢。-this is an IP core of blutooth.
usb
- USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control,
core_licenses_full
- 这个是XILINX公司FPGA的aurora，IP授权！！完全好用!-This is the XILINX' s FPGA-aurora, IP licensing! ! Totally easy to use!
i2c_latest.tar_1
- I2C的OPEN CORE 的代码，很使用，可以直接改参数-I2C open core ip。verilog
usb2
- USB 2.0 IP Core for USB Interfacing
ISP1362-IP
- ISP1362的IP核用在USB 控制上可与PC通讯，作为SOPC的IP核-ISP1362' s USB IP core used in the control of communication with PC as the IP core SOPC
shiyanbaogao
- 了解ISE平台的基本环境，编译程序，在MC8051 IP核中，要求实现：增加PLL锁相环，扩大内部RAM，定时器，串口和外部中断等资源，并增加乘法器和除法器的功能。-ISE platform to understand the basic environment, compiler, the MC8051 IP core, the requirement to achieve: increased PLL phase-locked loop, expanding the internal RAM
USB-1.1-IP-CORE-VHDL
- USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code
uart-IP-Core
- 串口的FPGA VHDL的IP核 可以直接调用使用-Serial FPGA VHDL IP core can be called directly use
51
- 完整的8051的IP核，用VHDL语言描述-the ip core of c8051,described in VHDL language
xfft_v8_0_bitacc_cmodel_lin64
- FFT的C模型，用于仿真FFT IP Core的功能-Bit Accurate C Model of Fast Fourier Transform
ethmac10_100M
- 以太网IP Core 它实现10/100 Mbps的MAC控制器功能。它是在IEEE802.3和802.3u 标准下设计实现的。-The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary to implement the Layer 2 protocol of
usb1.1_sim_465206689
- usb1.1_sim_465206689 IP核开发以及其调用。-usb1.1_sim_465206689 IP core development, as well as its call.
PG007_Xilinx RapidIO IP阅读笔记
- srio pg007 中文，iP核介绍和仿真步骤(The iP core is introduced and simulation steps)