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uart
- 开源的串口通信程序，用vhdl 编写的，已通过测试，在DE2的开发板上能够运行。
uart.rar
- 实现串并口通信,共有发送和接受两个模块。,Strings parallel to achieve communication, send and receive a total of two modules.
uart
- 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
UART
- 本人自己编写的FPGA异步串口通信模块（UART），基于QuartusII环境，verilog语言编写，包含仿真和全部程序及说明，验证通过，具有很好的稳定性和参考价值！-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the pr
uart16550
- uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can b
UART
- 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
uart
- 通用穿行通信控制器，可以直接使用，在quartsII下开发-GM through communications controller, can be directly used in developing quartsII
UART
- 使用方法： uart编程,拷贝到硬盘，用ISE打开工程文件即可-Usage: uart programming, copied to the hard drive, open the project file with ISE can
uart
- 串口通讯rs232,时钟频率为40Mhz,波特率为19200,没有奇偶校验,在xilinx XC3S200A板子上验证过.-Serial communication rs232, clock frequency of 40Mhz, the baud rate to 19200, no parity, in the board on xilinx XC3S200A verified.
pro104_uart
- uart的代码，经实际运行可以通信，是xilinx uart 代码的改进，网上的xilinx uart代码有很多bug，用此代码可以改进运行。-UART code, the actual operation can be communication, xilinx uart code are improved, xilinx uart code online has a lot of bug, the code can be improved with this operation.
uart
- uart协议、实现、验证，基于wishbone协议，工业标准为16550A-UART protocol, implementation, verification, based on the Wishbone protocol, the industry standard for the 16550A
71477212NiosII_uart
- 串口sopc uart实现串口功能，包含帧的开始字节，命令字节-Serial sopc uart serial implementation features, including frame start byte, command byte
rxd
- VHDL语言写的UART通信接收端程序，适用于RS232协议-VHDL language the receiving end of the UART communication procedures, applicable to RS232 protocol
uart_zhiwen
- RS232的UART编程，包括波特率发生器模块，串口接受模块，串口发送模块-RS232 programming the UART, including the baud rate generator module, serial module to receive, send serial module
uart16750_latest.tar
- Implements a 16550/16750 UART core
uart_module
- 实现精简的uart串口,格式起始位+8bit数据位+可配置的奇偶校验位+停止位-implement a smart UART interface
UARTcode
- 串口UART通用异步接收/发送器的VHDL 源代码-Serial UART code
xapp345_verilog
- IrDA & UART Design (Verilog)
UART16550
- UART控制器，集成FIFO，寄存器，数据位宽8位-UART controller, with FIFO, register, databus 8bits
RS232
- simple example for uart on fpga