用于FPGA的按键消抖的Verilog文件，经过modelsim仿真和下板验证。-Verilog file for FPGA key debounce, after modelsim simulation and verification under the plate.

按键输入四位数，长按功能键排序或者求最大公约数并显示在数码管上(Key input four digit, press function key sequence or for the common denominator and digital tube display)