搜索资源列表
usb_ctr
- usb的verilog 代码。对理解usb的原理有很大帮助，并可以在nc环境下仿真。-usb the Verilog code. Usb to understand the principle is very helpful, and to be nc simulation environment.
usb
- 实现了USB接口。介绍了如何使用VERILOG语言实现USB的程序设计。
usbfree_core
- 完整的usb freecore，全部用verilog编写
logic
- SRAM和USB芯片FT245的VERILOG逻辑控制
FPGA与USB通信的测试代码
- FPGA与USB通信的测试代码，包括FPGA中的程序（Verilog编写）和PC机上的主控程序以及USB固件程序。,FPGA and the USB communication test code, including the FPGA in the procedure [Verilog prepared] and PC-control procedures, as well as the USB firmware.
Verilog_CY7C68013-SLAVE-FIFO
- 用VERILOG 编写 CY7C68013 usb数据采集SLAVE FIFO模式驱动程序 ，已验证过-Prepared with the VERILOG CY7C68013 usb data acquisition SLAVE FIFO mode driver, has proven
usbFPGAconnect
- 该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序，FPGA上的VERILOG通信程序。-The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, incl
USBipcore
- usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
usb_funct
- USB 2.0 verilog源代码,内包含详细文档资料。-USB 2.0 verilog source code, which contains detailed documentation.
USBtoUART
- USB转串口资料,相关USB芯片介绍、程序等-USBtoUART.rar
pci-verilog
- USB及PCI总线设计的一些源代码（经测试）-USB and PCI bus design some of the source code
usbjtag
- 用于USB blaster下载线设计的JTAG仿真用的Verilog源码-For the USB blaster download cable design simulation using Verilog source JTAG
module-usb
- usb verilog code for transmitter
USB
- 此例程是基于FPGA的USB控制器实例，主要功能为通过FPGA芯片控制USB芯片，实现开发板和PC机之间的USB接口数据通信，来模拟一个硬件加密设备的功能。用Verilog语言实现。-This routine is an instance of the USB controller based on FPGA, the main function is to control USB chip by the FPGA chip, implement the USB interface for da
usb
- pc与fpga之间的数据传输 在fpga上有一个usb芯片cy68013 用verilog来对usb芯片进行控制-the communication between pc and the fpga，these is a cy68013 on the fpga，which is controled through verilog
test_usb_q
- USB的测试代码已经证明是好使的，使用Verilog编程，放心使用-USB Verilog
USB-IPcore-Verilog
- USB IP 核设计，Verilog，ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened
USB
- verilog 实现USB传输功能，包括A/D转换、驱动程序等-vrilog usb
fpga_slavefifo2b_verilog
- fpga控制USB接口数据收发，包含verilog 仿真代码和调试工程(fpga control usb3.0, modelsim simulation, verilog language)
kwmltable-operand
- RS码的FPGA实现,verilog语言形式,好参考资料()