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serialcomvhdl
- 一个串行通信的例子，用vhdl实现。包括发送接收，分频等多个模块-Example of a serial communication with the realization of vhdl. Including the transmission of the reception, a number of modules, such as Frequency Division
clock
- 由锁相环(PLL)产生所需的2分频与4分频时钟8分频时钟 clk.qpf为可执行主程序 -By the phase-locked loop (PLL) have the necessary 2-and 4-frequency clock frequency of 8 minutes for Executable clk.qpf main clock
gmsk_2
- 实现2M数据速率的GMSK调制，时钟频率20M，2分频后作为移位寄存器-2M data rate to achieve the GMSK modulation, the clock frequency of 20M, 2 minutes after a shift register frequency
FDIV10E
- ISE下用vhdl语言实现10分频及测试-ISE achieve 10 points lower frequency and test vhdl language
DIV
- 占空比为50%的七分频电路，实用基于VHDL语言，仿真工具是ISE(Duty cycle of 50% of the seven frequency circuit)
FRECHANGE
- 基于vhdl的分频器程序。可以将50mhz的频率分为1hz(clk divice program base on fpga)