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dsp48macro_macfir
- xilinx embedded system: FIR design example.
数字时钟管理器，xilinx公司开发板集成时钟
- 数字时钟管理器，xilinx公司开发板集成时钟，实现分频、倍频等功能。-Digital clock managers, xilinx development board integrated clock divider, multiplier, and other functions.
mpeg_4_encoder_ds511
- Xilinx的MPEG-4 Part 2 Simple Profile 编码核说明-Xilinx
hardh264
- 一个硬件H264编码的VHDL源码，用于FPGA开发，适合IP摄像头等视频设备输出数据的编码。用Xilinx工具测试过，但代码不只是用于Xilinx。-A hardware h264 video encoder written in VHDL suited to IP cameras and megapixel cameras. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools
MAC_MPEG2_AV
- MPEG2 編碼解碼的verilog 代碼 可在XILINX FPGA上使用-Mpeg2 Encode/Decode on Xilinx FPGA Board
video_capture_rev_1_1
- 视频图像的捕捉系统的实现，主要是基于XILINX系统的实现-Video image capture system implementation is mainly based on XILINX System
VGA
- VGA 640x480 controller using FPGA Xilinx using Xilinx ISE 10
VDMA
- Xilinx Xapp1205 VDMA参考设计-Xilinx Xapp1205 VDMA Reference Design
nysa_sata_latest.tar
- The Xilinx CORE Generator™ is used to create a single-lane PCIe Endpoint Plus design. The generated PCIe system contains the PCIe endpoint plus block, GTP tiles, block RAMs, and clock and reset modules. The tutorial below shows how to create the
h265enc_v1.0
- 用vhdl语言编写的h.265编码器，可用于xilinx或altera的fpga(h.265 encoder written by vhdl. It can be download to xilinx or altera's fpga)