搜索资源列表
CIC_deci4.rar
- cic抽取滤波器ip核,用于射频采样数字下变频模块的核心数字信号处理部分.此ip核已经过ise10.2验证,CIC decimation by 4 filter,used in Direct RF sampling of GPS signal. the core dsp block in a frondend design
digitaldown-conversion.rar
- FPGA实现数字下变频,仅供大家参考,希望有用。,Use FPGAto achieve digital down-convertion.For your reference, I hope it can be useful for you
DDC.rar
- verilog语言实现的数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用,好用。,Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.
ddc_FPGA
- 简要介绍了数字下变频的设计,通过采用xilinx的ise软件,ipcore的调用实现-Briefly introduced the design of digital down conversion, through the use of ise the xilinx software, ipcore call the realization of
project_UHF_ddc
- vhdl语言写的数字下变频的实现,整个工程文件,xlinx ise用的-VHDL language written in the realization of digital down conversion, the whole project file, xlinx ise used
DDC_CIC
- 用CIC 和 FIR Filters设计的数字下变频器,DSP Builder6.1版工程文件-Using CIC and FIR Filters Design of Digital Down Converter, DSP Builder6.1 version of project file
FIR_TEST
- 应用matlab 软件设计了下变频器中的CIC、HB、FIR滤波器等核心模块,并将各模块融为一体从软件实现的角度完成了对系统的搭建和功能仿真。-About such key algorithms as CIC, HB, FIR of each module in down- conversion, discussion, abstraction and summarization are given in this paper. Using the MATLAB software, we des
tes_amp_80_0314
- 基于dsp builder的数字下变频器,IP核做的-digital down converter,degigned in matlab
RealizationofdigitaldownconversionbyFPGA
- 介绍在FPGA 器件上如何实现单通道数字下变频(DDC)系统。利用编写VHDL 程序和调用部分IP 核相结合的方法研究了数字下变频的FPGA 实现方法,并且完成了其主要模块的仿真和调试,并进行初步系统级验证。-Introduced in the FPGA device on how to achieve the single-channel digital down conversion (DDC) system. VHDL procedures and the use of the prepa
verilog_FPGA_DDC
- 这是一个用verilog HDL实现的实现数字下变频的源代码。-This is a verilog HDL used to achieve the realization of digital down conversion of the source code.
nco
- 基于DSP builder搭建的DDS模块,可以用在数字下变频中的NCO等-Based on DSP builder to build the DDS module can be used in digital down-conversion of the NCO, etc.
cic_dec_8_five
- CIC抽取滤波器,抽取系数8,verilog版本,用于数字下变频-CIC decimation filter, extraction coefficient of 8, verilog version, for digital down-conversion
fir_dec3
- FIR抽取滤波器,抽取系数3,Verilog版本,数字下变频-FIR decimation filter, extraction coefficient of 3, Verilog version of the digital down-conversion
CIC
- 五阶CIC滤波器,用于降低数据传输速率。数字下变频技术不仅是软件无线电核心技术之一,还是中频数字化接收系统重要组成部分。数字下变频技术中广泛用到级联积分梳状滤波器(CIC滤波器)-CIC filter
DDC_Ver1.0
- 数字下变频(DDC)在如今基于软件无线电的架构中对系统的整体性能决定性的影响,代码为基于Matlab的4通道DDC程序,程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值-Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code
shuzixiabianpin
- 数字下变频中cic滤波器,级联三级,主要功能是抽取滤波,及重要参考资料,包括数字下变频论文-Digital down conversion of cic filter, cascade three-level main function is to extract the filter, and important reference materials, including digital down conversion papers
61EDA_C2111
- 数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用,好用。--Verilog language implementation of the digital do
DDC
- 文介绍了数字下变频的组成结构,并通过一个具体的实例,给出了FPGA实现的具体过程。-Paper describes the digital down conversion of the structure, and through a specific example, given the specific FPGA implementation process.
Digital-IF-Receiver-Based-on-FPGA
- 基于FPGA的数字中频接收机设计与实现。近年来雷达行业提出了软件雷达的概念,数字技术在雷达中的广泛应用已成为一种必然趋势。现代雷达系统对接收机提出了更高的要求,数字接收机技术已成为实现高精度宽带雷达接收系统的一种有效途径。研究了数字接收机的相关理论和技术,介绍了数字下变频,数控振荡器、级联积分梳状滤波器和抽取。给出了一种基于FPGA的数字中频接收机实现方案,进行了分析和仿真,给出了测试结果-Design and Implementation of Digital IF Receiver Base
数字下变频FPGA 程序
- 数字下变频程序,完整的程序编译文件,适应于雷达信号处理,从ADC直接下变频