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muxplusii --vhdl 经典程序
- 用VHDL编写的数字时钟,可变宽度脉冲产生器-prepared using VHDL digital clock, Variable width pulse generator, etc.
LED.VHDL
- LED控制VHDL程序与仿真 分别介绍采用FPGA对LED进行静态和动态显示的数字时钟控制程序-LED control procedures and VHDL simulation briefed on the use of FPGA LED static and dynamic significantly the figures show clock control procedures
szsz
- 数字时钟vhdl实现
基于VHDL 的数字时钟
- 用VHDL实现时钟的显示,包括七段数码管和lcd1602字符液晶,可以显示十分秒,年月日
vgaclock.rar
- vga显示的数字时钟,用mif文件实现,用以大家学习交流,vga display digital clock, with the realization of mif file for them to learn from the exchange of
vhdl
- 基于vhdl的数字时钟;24制,带有定时,闹钟等功能。-VHDL-based digital clock 24 system, with time, alarm clock functions.
clock
- 用verilog语言实现数字时钟,有注释,规范-Digital clock using verilog language, there are notes, specifications
digitalclockvhdl
- EAD设计VHDL语言环境数字时钟数码管显示方案,包括时间设置、调整等。-VHDL language environment EAD design digital digital clock display, including time for setup, adjustment.
vhdl-digital-clock-design
- 设计一个具有特定功能的数字电子钟。准确计时,以数字形式显示h、min、s 的时间。小时的计时要求为二十四进位,分和秒的计时要求为六十进位。 该电子钟上电或按键复位后能自动显示系统提示00-00-00,进入时钟准备状态;第一次按电子钟功能键,电子钟从0时0分0秒开始运行,进入时钟运行状态;再次按电子钟功能键,则电子钟进入时钟调整状态,此时可利用各调整键调整时间,调整结束后可按功能键再次进入时钟运行状态。 -Designed with a specific function of a dig
Digital_Clock_VHDL
- 使用VHDL开发的简易数字时钟软件,可以作为初学者熟悉定时器应用的实例程序。-Use VHDL to develop a simple digital clock software can be used as timers for beginners familiar with examples of the application process.
myled4
- 四位动态数码管显示数字时钟的分位和秒位。工具:Quartus ii 6.0 语言:VHDL-4 shows the number of dynamic digital tube digital clock and seconds bit. Tools: Quartus ii 6.0 Language: VHDL
ask100
- 时钟同步模块:通过时钟同步模块,将模拟前端提取的时钟信号和数据进行同步,使得数字后端可以正确读取数据。-Clock synchronization module: The clock synchronization module, the analog front-end of the clock signal extraction and data synchronization, making the number of back-end data can be read correctly
vhdl-clock
- 数字时钟的VHDL课程设计 涉及到的几个要点有 分频模块 时分秒模块 扫描模块 显示模块-Digital Clock Design of VHDL course of a few key points related to one of those who every minute frequency module module module module scan
eetop.cn_digital_clock
- 基于VHDL的数字时钟设计课件,简单,实用-VHDL-based Digital Clock Design Courseware
Digitalclock_vhdl
- VHDL语言编写的数字时钟代码,环境quartus-Digital clock written in VHDL code, the environment quartusII
shuzishizhong
- 本实验实现一个能显示小时,分钟,秒的数字时钟。数字时钟-The experimental realization of a can display hours, minutes, seconds, the digital clock. Digital Clock
clock
- 基于VHDL硬件描述语言设计的多功能数字时钟的思路和技巧-VHDL hardware descr iption language based on multi-functional digital clock design ideas and techniques
数字钟
- fpga课程中用vhdl语言编写的数字钟 输出到板子上是,就是一个数字时钟
clock
- 数字时钟,用VHDL语言设计,能调时间,整点响铃(Digital clock, designed in VHDL language, can adjust the time, the whole bell ring)
LED控制VHDL程序与仿真
- LED控制VHDL程序与仿真 分别介绍采用FPGA对LED进行静态和动态显示的数字时钟控制程序。