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除法器
- 通过用硬件描述语言(VHDL)描述除法器,并进行模拟验证,加深对二进制数运算方法的理解。 设计平台:MaxPlusII 压缩文件内有详细设计报告 -by using Hardware Descr iption Language (VHDL) Descr iption division, and conduct simulation shows that the binary number deepen understanding of the operation. Design Pl
divider.8位的除法器
- 8位的除法器。用VHDL语言进行设计实现。,8-bit divider. With VHDL design languages.
c18_divider.rar
- 精通verilog HDL语言编程源码之4--常用除法器设计,Proficient in language programming verilog HDL source of 4- Common divider design
single_clock_divider.rar
- 单周期除法器,速度快,满足频率要求,使得单周期内得到除数,Single-cycle divider speed, to meet the frequency requirements
div(FLP).rar
- 是Nios II處理器下客製化指令的一個32位元浮點數除法器,可將兩IEEE 754格式的值進行相除,Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
div.rar
- 除法器实验 verilog CPLD EPM1270 源代码,Experimental divider verilog CPLDEPM1270 source code
divider
- 移位快速除法器,通过一次移4位试商实现快速除法功能,较普通减除法器有及其巨大的效率提升-Divider rapid shift by a shift to four test functions of rapid division, as compared with ordinary objects have less efficiency and its huge
除法器的设计本文所采用的除法原理
- 除法器的设计本文所采用的除法原理是:对于八位无符号被除数A,先对A转换成高八位是0低八位是A的数C,在时钟脉冲的每个上升沿C 向左移动一位,最后一位补零,同时判断C的高八位是否大于除数B,如是则C的高八位减去B,同时进行移位操作,将C的第二位置1。否则,继续移位操作。经过八个周期后,所得到的C的高八位为余数,第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the p
32_16div
- 这是一个简单的除法器(32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction
chufaqiziliao
- 除法器资料,做除法器的朋友们不可或缺的好论文啊。-Divider information, so the divider indispensable good friends ah paper.
divide
- 除法器-Divider
div16
- 十六位的除法器,采用verilog hdl-16 of the divider using verilog hdl
baweichufaqi
- 介绍了利用VHDL实现八位除法,采用层次化设计,该除法器采用了VHDL的混合输入方式,将除法器分成若干个子模块后,对各个子模块分别设计,各自生成功能模块完成整体设计,实现了任意八位无符号数的除法。 -Introduced the use of VHDL to achieve eight division, the use of hierarchical design, the divider using VHDL mixed-input methods, will be divided in
divide
- Verilog hdl语言的常用除法器设计,可使用modelsim进行仿真-Commonly used languages Verilog hdl divider design, can use the ModelSim simulation
dividend4
- 本设计是一个八位被除数除以四位除数,得到不超过四位的商的整数除法器。被除数、除数、商和余数都是无符号整数。-The design is an eight dividend divided by the divisor of four, to be not more than 4 business integer divider. Dividend, divisor, and remainder are unsigned integers.
dividers
- verilog格式的除法器,试过了,很好用,再也不要为触发器发愁了-Verilog format divider, tried, very good, and no longer for the flip-flop not to worry about the
Divider
- 一个用vhdl硬件描述语言实现的一个比较简单的除法器-an divider using vhdl
juzhenqufaqi
- 基于FPGA单精度浮点除法器的实现,有一些源代码,仅供参考。-FPGA-based single-precision floating-point divider realization, there are some source code, for reference purposes only.
chufaqichengxu
- 除法器程序,除法器模块,定点数除法的相关代码。-Divider procedures, divider module, the related fixed-point code division.
HG_chufaqi_clajiafaqi
- VHDL基-16位的无符号除法器,超前进位加法器可改位数。-VHDL-based-16 bit unsigned divider, CLA can be the median.