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AES AES快速算法和蓝牙设备中用的E0算法
- AES快速算法和蓝牙设备中用的E0算法(用于加密)、E1算法、E2算法、E3算法（用于密钥管理和鉴权等）等,AES fast algorithms and Bluetooth devices using the E0 algorithm (for encryption), E1 algorithm, E2 algorithm, E3 algorithm (for key management and authentication, etc.)
aes
- verilog实现的AES-128加解密程序，FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
aes
- 高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
FPGA_128_AES_decryption
- 以FPGA具體實現的128-bit AES decryption，包括介紹文件以及源碼。-FPGA-based 128-bit AES decryption
AES_cs
- In cryptography, the Advanced Encryption Standard (AES) is a symmetric-key encryption standard adopted by the U.S. government. The standard comprises three block ciphers, AES-128, AES-192 and AES-256, adopted from a larger collection originally publi
LPC_IAP_FlashLoader_145x
- LPC2368 IAP_Flashloader with AES-128
FPGA--AES-algorithm
- 本文介绍了AES 数据加密结构, 以及相关的有限域的知识及简单运算, 提出了一种用FPGA 高速实现AES 算法的方案, 该方 案设计的加密模块支持AES 标准的三种密钥长度: 128,192,256, 支持ECB, CBC, CTR 三种工作模式, 即支持feedback 和non- feedback 两种模式, 最后给出了本设计的性能指标-This article describes the AES data encryption structure, as well as the
FFT-C
- C语言实现FFT算法，思维清晰，技巧行较强。-AES encryption algorithm (128) bit Verilog implementation, modular design, easy to understand.
AES64plus_v1.00
- 针对C64++ DSP优化的128位AES加密源码-128 bits AES Algorithm for C64++ DSP platform
OOO
- AES 低资源利用率的加密解密，状态机的使用，128位的-Encryption and decryption, the state machine of low resource utilization using AES 128-bit
AES
- AES 数据加密例程 128位加密 安全可靠-AES data encryption routine 128 bit encryption security and reliability
AES 128 CBC Decryption
- Block mode related AES implement on GHDL
AES 128 CBC Encryption
- Block mode related AES algorithm
AES 128 ECB Decryption
- Block mode related AES-EBC Encryption
AES 128 ECB Encryption
- Block mode related AES-EBC Decryption
Package for AES-128
- Block mode related AES Package
aes128-hdl-master
- Verilog AES hdl key 128 bit code and decode
STM32AES
- 基于STM32F103实现AES算法的工程，支持128,196,256位AES(Based on STM32F103, AES algorithm is implemented, supporting 128196256 bit AES.)
aes_128pprm3
- 基于PPRM3S盒的128位AES密码算法Verilog代码(Verilog code for 128 bit AES cipher based on PPRM3S box)
AES算法硬件实现
- AES算法硬件实现，使用SAKURA开发板，128位密钥的AES算法