搜索资源列表
tb_ahb_master.rar
- this is a AMBA AHB code for master.,this is a AMBA AHB code for master.
CODE.rar
- AHB总线下的slave ram的verilog代码,AHB bus slave ram verilog
AHBtoAPB.rar
- amba总线桥:ahb to asb!verilog hdl文档加代码，非常全，soc,amba bus bridge: ahb to asb! verilog hdl code for the document plus a very full, soc
AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_R
dma_ahb_latest.tar
- this shows the ip code for dma controller of amba ahb in vhdl.
ahb_ram
- AHB接口的ram控制器，可靠性非常强。除了两个周期内发生读到写或写到读的极限情况（一般处理器设计中不会有这种传输方式），其他传输方式完全没有问题-AHB interface ram controller, reliability is very strong. In addition to occurring in two cycles read or write read write the limit (usually processor design will not have such
AMBA-AHB-APB-BUS
- 常见ARM架构的AMBA、AHB、APB总线的介绍，对ARM的总线有个清晰的了解，对各模块的关系也可深入了解-Common ARM architecture AMBA, AHB, APB bus introduction of ARM' s have a clear understanding of the bus, on the relationship between the modules can also be in-depth understanding of
DW_8b10b_enc.v.tar
- amba ahb protocol with test benches
ahb2wishbone_latest.tar
- opencore ahb to wishbone bus verilog code
ahb_master1
- this is a code of AMBA AHB master protocol in verilog
New
- amba ahb master decoder
apb_bridge
- arm ambm 2.0 primecell算法 ahb 与 apb通讯的转换模块-arm ambm 2.0 primecell algorithm ahb conversion and communications module apb
CAST_sdr_sdram_ctrl-xact
- Single Data Rate Mobile SDRAM Controller Core with AHB Interface
AMBA_V2.0_CN
- ARM公司高级微控制器总线体系（Advanced Microcontroller Bus Architecture AMBA ）规范中文版，包括ASB，AHB，APB总线-Senior ARM microcontroller bus system (Advanced Microcontroller Bus Architecture AMBA) specification, including the ASB, AHB, APB bus
masterdecoder
- AHB总线协议 Master实现代码，对于开发AHB总线的很有帮助-AHB bus protocol to achieve Master code, very helpful for the development of AHB bus
AHB
- 用VHDL编写的AMBA总线的AHB代码-Written with the VHDL code for AMBA bus AHB
AHB
- 基于混合优先权算法的AHB总线仲裁器的设计-Hybrid algorithm based on priority AHB bus arbiter design
AHB-BUS-AND-SLAVE-CODE-USING-VERILOG
- AHB总线下的slave代码verilog-AHB BUS AND SLAVE CODE USING VERILOG
ahb
- verilog实现AHB总线上的主从控制，在fpga上验证通过(Verilog realizes master slave control on AHB bus and verifies it on FPGA)
AHB-task-slave-master
- ahb master行为级模型，ahb slave模型(AHB master behavior level model, AHB slave model)