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AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型,主要包括5个部分:AHB总线仲裁器,AHB-APB总线桥接器,AHB总线上从设备ROM模型,AHB总线上从设备RAM模型,参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_R
AHB
- 基于混合优先权算法的AHB总线仲裁器的设计-Hybrid algorithm based on priority AHB bus arbiter design
AHB-Arbiter-Module
- AMBA2.0版本AHB总线仲裁器设计方面的技术支持,参考ARM公司AMBA技术手册。对AHB仲裁电路的接口、基本逻辑等方面进行介绍。-AMBA2.0、AHB Arbiter Module
AHBArbiter
- AMBA ahb总线协议的arbiter模块源代码,verilog编写,适合新手学习使用。-this is a code of AMBA AHB arbiter protocol in verilog
ahb
- 基于AMBA2.0的AHB 总线,包括arbiter,decoder,Muxs2m,Muxm2s-Based AMBA2.0 the AHB bus, including the arbiter, decoder, Muxs2m, Muxm2s
ahb_system_generator_latest.tar
- AHB system generator. This file is a part of a system generator for AHB system. it is VHDL code for the AMBA arbiter.
AMBA
- AMBA总线的Verilog语言模型,主要包括5个部分:AHB总线仲裁器,AHB-APB总线桥接器,AHB总线上从设备ROM模型-AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave