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Coefficient Reload FIR Filter Design Example v7.2
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8阶对称系数FIR滤波器分布式算法的实现代码-8-order FIR filter symmetric coefficient distributed algorithm implementation code
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:介绍了基于FPGA的FIR数字滤波器的设计与实现,该设计利用Matlab工具箱设计窗函数计算FIR滤波器系数,并通过VHDL层次化设计方法,同时FPGA与单片机有机结合,采用C51及VHDL语言模块化的设计思想及进行优化编程,有效实现了键盘可设置参数及LCD显示。结果表明此实现结构能进一步完善数据的快速处理和有效控制,提高了设计的灵活性、可靠性和功能的可扩展性。
-: This paper presents FPGA-based FIR digital filter design and
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文章提出了基于多带语减法改进的增强系统，并在TI会司的浮点处理器TMS320C6713上实现。改进的多带语减法将信号频语非线性的分成4个互不重叠的频带， 每个频带分别做不同系数的语减运算， 因此能很好的滤除有色噪声。工程实现证明此设计能有效的抑制色噪声和音乐噪声， 即便在低信嗓比环境也能有较好增强效果.-In this paper, a language based on multi-band subtraction improved augmentation system, and TI wi
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CCS环境下系数对称FIR滤波器的实现方法。-CCS environment symmetrical coefficient FIR filter implementation.
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线性缓冲区FIR滤波器设计，可利用MATLAB产生系数，利用CCS开发环境，调试成功！-FIR filter design for linear buffer can be generated using MATLAB coefficient, the use of CCS development environment, debugging success!
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用ADSP21062实现快速FIR滤波器算法
压缩包内有源代码和说明-Analog Devices, Inc. DSP Applications P.O.Box 9106 Norwood, MA 02062
Christoph D. Cavigioli, updated by Michael Hennerich July-10-2001
Files required for a Finite impulse Response Filter example
fir
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32位乘法，将16位数据和系数扩展32位数，10抽头FIR滤波器-32-bit multiplication, the 16-bit data and coefficient of expansion of 32-digit, 10-tap FIR filter
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CIC抽取滤波器，抽取系数8,verilog版本，用于数字下变频-CIC decimation filter, extraction coefficient of 8, verilog version, for digital down-conversion
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FIR抽取滤波器，抽取系数3，Verilog版本，数字下变频-FIR decimation filter, extraction coefficient of 3, Verilog version of the digital down-conversion
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题为基于CSD编码的FIR数字滤波器设计.该滤波器具有线性相位,系数减半.采用VHDL语言编写.是我们EDA课程的作业,得了优.希望对大家有用-Entitled based on CSD code FIR digital filter design. That the filters have linear phase, coefficient half. Using VHDL language. Is the EDA program operations, got excellent. Hop
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11阶fir数字滤波器的verilog程序设计，线性相位，系数量化处理-11 order of fir digital filter verilog programming, linear phase, the coefficient quantization
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Implementation of FSK modulation in DSP: the coefficient file contains coefficients of a filter generated by matlab: Code executable without bugs, and source files are in assembler
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基于FPGA的32阶FIR滤波器设计，研究了一种采用FPGA实现数字滤波器硬件电路方案；讨论了窗函数的选择、滤波器的结构以及系数量化问题-32 order FIR filter design based on FPGA, an FPGA implementation digital filter hardware circuit program discussed the choice of the window function, the structure of the filter co
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利用Verilog HDL语言实现公共表达式交叉系数滤波器-Using Verilog HDL language implementation public expression cross coefficient filter
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PIC单片机的CCP功能
//220V的交流电源直接用电阻限流,经光耦隔离,形成脉冲送到CCP2,
//CCP2模块的捕捉功能,设置为每16个上升沿捕捉一次,相当于平均滤波,目的是为了减小误差
//TMR1计数的分频系数计算:假设电源为50Hz,即一个周期为20ms,16个周期为320ms
//320ms=320000us,单片机用4MHz晶振,指令周期为1us,设TMR1的分频系数为K:65536×K=320000
//得K=4.88,取K=8,即TMR1的预分频系数设为1
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利用MATLAB提取相关系数，按照matlab的滤波思路进行编写的IIR滤波程序，已经证明好用！-MATLAB is utilized to extract the correlation coefficient, according to the writing of IIR filter MATLAB filtering ideas for program, it has been proved useful!
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此程序应用了流水线技术来实现IIR滤波器，它是由一个非递归部分和一个具有延迟为2和系数为9/16的递归部分构成。-The procedure applied to the pipeline techniques to achieve an IIR filter, which consists of a non-recursive portion and having a delay of 2 and a coefficient of the recursive part 9/16 constit
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FIR FILTER USING FCSD TECHNIQUE FOR REPRESENTING COEFFICIENT
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FIR filter design using Matlab Coefficient file and RTL design for FIR filter Design
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