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clock
- 数字钟设计，有分秒显示，上下午显示，可下载到FPGA板子上进行数字显示哦-Digital clock design, there are minutes and seconds display, on the afternoon of shows can be downloaded to the FPGA on the board figures show Oh
gelishurumokuai(product)
- 8路隔离数字量输入模块，具有8路数字量输入，通信接口间采用光电隔离方式设计，不易受各种电磁干扰，大大提高通信的可靠性、安全性和保密性，支持MODBUS－RTU 通讯协议；可与多种品牌的PLC、RTU及工控组态软件进行网络通讯，广泛应用于分布式电力系统监控、各种工业自动化测控等系统中。-8-channel isolated digital input module with 8 digital inputs, communication interface between the use of p
MCU_Digital_Clock
- <基于单片机的数字钟设计> 个人做的毕业设计,带Protel图,源代码用proteus软件仿真通过,附有毕设论文-<Based on single-chip digital clock design> individuals do graduate design, with Protel map, the source code through the use of Proteus software simulation, complete with paper-ba
Digital_Clock
- 使用汇编语言实现数字时钟设计，用7seg完成显示，并可以通过button对时钟进行调整。并包括系统仿真原理图，适合做设计者使用-The use of assembly language to achieve digital clock design, with the completion of 7seg show, and can adjust the button on the clock. And includes system simulation schematic diagram,
electric-8.08
- The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including: * Custom IC layout * Schematic Capture (digital and analog) * Textual Languages such a
new
- DS1302的1602时钟电路设计LED数码管时钟电路采用24h计时方式，时、分、秒用六位数码管显示，其中小时、分、秒之间用小数点分开。该电路采用AT89C52单片机和DS1302实时时钟芯片，使用5V电源进行供电，使用3个按键进行调时，调整过程中被调节的分钟或时钟将进入闪亮状态，看上去非常直观，另外，本设计还具有快速调时功能，当按键一直被按下时，便进入快速调时状态。[-DS1302 circuit design of the 1602 clock LED digital tube clock
DDC_CIC
- 用CIC 和 FIR Filters设计的数字下变频器，DSP Builder6.1版工程文件-Using CIC and FIR Filters Design of Digital Down Converter, DSP Builder6.1 version of project file
ElectronicCodeLock
- 设计一个通用电子密码锁，具体功能如下：[1]数码输入 [2]数码清除 [3]密码更改 [4]激活电锁 [5]解除电锁-The design of a universal electronic code lock, the specific features are as follows: [1] digital input [2] Digital Clear [3] Password Change [4] to activate electric lock [5] the lifting
BIYEDEJI
- 本设计为基于MSP430单片机的两线制一体化智能温度变送器模块，它支持工业上常用的热电阻与热电偶传感器，同时它还能够通过简易的RS-232口进行参数设定。系统主要由电源模块、AD采样模块、MCU模块、通讯模块及就地指示模块等部分组成。软件上采用了限幅平均滤波、数字校准、迭代等方法，与硬件配合，获得了比较高的检测精度。该温度变送模块具有电路简单、 精度高、 超低功耗等特点，它可以很方便地安装到现场，实现对温度的实时检测，具有较好的实用价值。-The design is based on the i
paobiao
- 一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.
ebook_verilog_fine_state_machine
- Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
alu
- 设计带进位算术逻辑运算单元，根据74LS181功能表，用Verilog HDL硬件描述语言编程实现ALU181的算术逻辑运算功能，编辑实验原理图，在算术逻辑单元原理图上，将其扩展为带进位的算术逻辑运算单元，对其进行编译，并设计波形对其进行仿真验证，最后下载验证-Design into the digital arithmetic logic operation unit, in accordance with menu 74LS181 with Verilog HDL hardware desc
DS1302clockchip
- 使用数字式时钟芯片DS1302设计的电子时钟，Keil51实现，实际运行通过-The use of digital design of the DS1302 clock chip electronic clock, Keil51 achieved through the practical operation
PLL
- PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上； 顶层文件是PLL.GDF-Digital phase-locked loop PLL is the design source code, which, Fi is the input frequency (receive data), Fo (Q5) is
Alford
- Alford.C. Digital.Design.VHDL.Laboratory.Notes_(1996)
DualDSPbasedembeddedvisualfeedbackcontrolsystemfor
- 为了满足多种电力电子变换器对其控制平台的不同要求,缩短开发时间,实现控制平台硬件的通用化和软件 的模块化,在基于双定点数字信号处理器(DSP)TMS320LF2407的大容量变换器专用控制平台的基础上, 提出了电力电子变换通用控制平台的设计目标。描述了基于定点和浮点DSP(TMS320F2812和TMS320VC33)的通用 控制平台各单元的设计方法。介绍了基于MATLAB实时工具箱(RTW)的调试方法。实验结果验证了设计和调试方法 的正确性和可行性,该通用控制平台达到了设计目标
FPGACPLDDigitalCircuitDesign
- FPGA & CPLD Digital Design Experience Sharing in Chinese
DigitalWatchVerilog
- 一个用Verilog实现的数字跑表的程序 希望对你的设计有帮助-With the realization of a digital stopwatch Verilog process of design you would like to help
FIR_TEST
- 应用matlab 软件设计了下变频器中的CIC、HB、FIR滤波器等核心模块，并将各模块融为一体从软件实现的角度完成了对系统的搭建和功能仿真。-About such key algorithms as CIC, HB, FIR of each module in down- conversion, discussion, abstraction and summarization are given in this paper. Using the MATLAB software, we des
shuzitongxinxitongjianmo04
- 基于CPLD_FPGA的数字通信系统建模与设计，本学习资料共分为4个部分，此为第四部分，供对数字通信系统建模和设计有兴趣的朋友学习参考。-CPLD_FPGA based on the digital communication system modeling and design, the learning materials is divided into four parts, this is the fourth part of the digital communication syst