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VerilogSynthesis
- 有关Verilog综合方面的教程，挺有用的-(Prentice) Verilog HDL--Guide to Digital Design & Synthesis (2nd.Ed.)
fir
- 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information i
FIR
- The first three examples illustrate the difference between RTL FSMD model (Finite State Machine with Datapath buildin) and RTL FSM + DataPath model. From view of RT level design, each digital design consists of a Control Unit (FSM) and a Datapath. Th
CPLD_portable_digital_storage_oscilloscope_hardwar
- CPLD的便携式数字存储示波器硬件平台设计-CPLD portable digital storage oscilloscope hardware platform design
stopwatch
- 数字秒表的VHDL代码。当设计文件加载到目标器件后，设计的数字秒表从00-00-00开始计秒。，直到按下停止按键（按键开关S2）。数码管停止计秒。按下开始按键（按键开关S1），数码管继续进行计秒。按下复位按键（核心板上复位键）秒表从00-00-00重新开始计秒。-The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stop
szdyb-proteus-CODE
- 利用proteus软件设计的数字电压表，包含有原理图和程序代码。-Proteus software design using the digital voltmeter, contains schematic and program code.
VHDL_digital_lock_design
- VHDL课程的源代码数字密码锁的设计与实现的实验报告，内附源代码-VHDL source code for the course digital code lock design and implementation of the experimental report, included the source code
microprocessor
- 一个微处理器的Verilog代码，根据英文书籍《数字设计与架构》中的例子而写，能够运行MIPS指令，能正确执行跳转指令。通过modelsim仿真，含测试代码。-Verilog code for a microprocessor, according to the English book " Digital Design and Architecture" was written in the example, to run MIPS instructions to jump
Electronic_stopwatch_features_plus_countdown
- 单片机做电子秒表。使用proteus仿真。设计要求：6位LED数码显示，计时单位为1/100秒。利用功能键进行启/停控制。其功能为：上电后计时器清0，当第一次（或奇数次）按下启/停键时开始计数。 当第二次（或偶数次）按下该键时停止计时，在一次按下启/停键时清0后重新开始计时。具有24秒减计数功能。 -SCM in the electronic stopwatch. Use proteus simulation. Design requirements: 6 LED digital dis
VLSI
- [電子書籍]利用verilog硬體程式語言來設計大型積體電路的經典書籍 "Digital VLSI Design with Verilog" 由淺入深值得一看 -[E-books] verilog hardware descr iption language used to design large-scale integrated circuit classic books " Digital VLSI Design with Verilog" Deep and worth
IIR(vhdl)
- 基于fpga的数字滤波器设计的vhdl源代码-Fpga digital filter design based on the vhdl source code
verilog-digitaldesign
- Verilog digital design
DesignReuse
- survey on digital design reuse gives information about the contents which can be reused
VerilogHDLsource
- Verilog HDL 高级数字设计源码-Advanced Digital Design Verilog HDL source
si_chapter
- SIGNAL INTEGRITY In the realm of high-speed digital design, signal integrity has become a critical issue, and is posing increasing challenges to the design engineers. Many signal integrity problems are electromagnetic phenomena in nature and he
digital_Oscilloscope
- 基于AT89S51的简易数字示波器设计 显示设备为有字库LCD12864-AT89S51-based design of a simple digital oscilloscope display device as a character LCD12864
DS12887
- ds12887，运用51单片机知识设计一个可以随意调节时间、带整点闹铃的时钟。（其中用到定时器、中断、按键、蜂鸣器、数码管或串口通信）-ds12887, using 51 single-chip expertise to design an adjustable time, with the whole point of the alarm clock. (Which use timers, interrupts, keypad, buzzer, digital control, or seri
Tutorial09_Clock
- 基于Spartan-3e的数码管显示时钟程序的设计，整个流程讲解详细。-A very important concept in digital design is that of the clock. A clock is used to synchronize systems in digital logic, and provides a convenient way to keep track of real time. Another equally important fact is
lcd_time
- 一个基于VHDL的多功能数字钟设计，能在LCD上显示时间，调整时间，整点报时，音乐为美妙的梁祝。-A VHDL-based design of multi-functional digital clock that can display time in the LCD, adjust the time, the whole point of time, music was wonderful Butterfly Lovers.
Design_of_digital_electronic_scale_classic_example
- Design of digital electronic scale classic example of information数字电子秤的设计信息的典型例子-Design of digital electronic scale classic example of information design information in digital electronic scales, a typical example of