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cfft
- CFFT是一个数据宽度和点数都可配置的基4 FFT core,用VHDL实现
FFT变换的IP核的源代码 VHDL~
- FFT变换的IP核的源代码 VHDL~-FFT IP core of the source code for VHDL ~
quartus 9.0 中FFT IP核的使用方法
- quartus 9.0 中FFT IP核的使用方法附带工程文件和用signaltapII抓到的波形,quartus 9.0 in FFT IP core attached to the use of engineering documents and the use of captured waveform signaltapII
fft_verilog.rar
- FFT IP core 源码 状态控制机,FFT IP core
Quartus_fft_ip_core.rar
- Quartus中fft ip core的使用(modelsim 仿真FFT ip core 结合QUARTUS II 联合调试),Fft ip core in Quartus use (modelsim simulation FFT ip core integration QUARTUS II Joint Commissioning)
fft
- 基于FPGA的51核，vhdl，FPGA开发。-FPGA-based 51-core, vhdl, FPGA development.
FFT_verilog
- verilog实现的FFT变换，经硬件测试其功能与Altera的FFT IP核相近-verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to
fft
- 基于VHDL语言编写的FFT程序，256点，旋转因子存在自己编写的ROM里面，乘法器和数据存储采用的是IP核-FFT-based program written in VHDL, 256 points, there is rotation factor which I have written the ROM, multiplier, and data storage is used in IP core
16Point-FFT
- 16点FFT VHDL源程序，The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input data is a vector of 16 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary component of a
studyFFTcore
- 调用FPGA的IP核实现FFT运算，在xilinx的vertex4sx55FPGA的实现-Call FPGA implementation of the IP core FFT computation, in the Xilinx implementation of the vertex4sx55FPGA
FFTVHDl
- 基于FPGA的fft实现 摘要：本系统基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核，代替传统DSP芯片或高性能单片机，实现了基于FFT的音频信号分析。-FPGA-based realization of the fft Abstract: This system is based on Altera Cyclone II family of embedded high-performance FPGA embedded IP core
fft_gen
- FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho &
cFFT
- CFFT is a radix-4 fast Fourier transform (FFT) core with configurable data width and a configurable number of sample points in the FFT. Twiddle factors are implemented using the CORDIC algorithm, causing the gain of the CFFT core to be differen
rax2
- rax2 fft implation the fft in verilog instance and in ise of xilinx it show how to istance fft core and the port used
fft
- fft程序，最初在单片机c8051f020上实现，“fft.c”是核心程序，很短，程序中x_real[N]是输入序列，输出保存在x_real[N]和x_imag[N]中-fft program, initially implemented on the MCU c8051f020, " fft.c" is the core program, very short, the program x_real [N] is the input sequence, the output
fft_ug
- altera的FFT IP核的用户手册，介绍了如何使用ALTERA IP核生成FFT核，如何设置参数并讲述了如何仿真，适用于通信方面的FPGA设计工程师，学生。-altera' s FFT IP core user manual describes how to use the ALTERA IP core generated FFT core, how to set parameters and describes how to simulate, for communications, FP
FFT
- verilog 实现FFT IP核的控制，借鉴给需要学习的朋友-verilog achieve FFT IP core control, reference to the need to learn a friend
FFT-module
- IP CORE ：FFT模块使用方法，内含源代码，希望对大家有帮助。-IP CORE: FFT module use, including source code, we want to help.
vhdl-fft-core
- FFT ip core，fft信号处理模块， VHDL语言编写-FFT ip core
fft
- 实现傅里叶算法，会得到电力参数。仔细体会算法中的含义，有助于理解再计算中的中坚变量(Fourier algorithm, you can get power parameters. Careful understanding of the meaning of the algorithm helps to understand the core variables in the calculation)