搜索资源列表
RS(32to28)encoderanddecoder
- RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
RS(204_188)decoder
- <Verilog HDL 语言编程》 RS(204,188)译码器的设计
RSdecoder.rar
- cpld/fpga RS(204,188)译码器的verilog程序,cpld/fpga RS (204,188) decoder of the Verilog program
rs_decoder_31_19_6_latest.tar.
- RS解码器的FPGA实现，有TestBench,RS decoder FPGA to achieve, there TestBench
RS-decoder
- RS 解码器主要包括以下5 个主要部分：伴随式计算、计算错误位置和错误值多项式、 钱搜索计算错误位置、福尼算法计算错误值和纠正解码输出。-RS decoder includes the following five main parts: With style, calculated error location and error value polynomial, Calculated error location search of money
final_decode
- rs解码器在fpga上的实现，采用的modelsim开发平台 -rs on fpga decoder in the realization of the development platform used in modelsim
c23_RS_decoder
- 精通verilog HDL语言编程源码9——RS(204,188)译码器的设计-Proficient in verilog HDL source programming language 9- RS (204188) decoder design
ps
- RS(204,188)译码器的设计 异步FIFO设计 伪随即序列应用设计 CORDIC数字计算机的设计 CIC的设计 除法器的设计 加罗华域的乘法器设计-RS (204188) decoder design of asynchronous FIFO design application design sequence was pseudo-CORDIC design of digital computer design CIC divider design Le Hua
rs-codec-8-16
- RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
rs_5_3_gf256_latest.tar
- this paper deal with rs decoder algorithm-this paper deal with rs decoder algorithm
rs_decoder204_188
- RS译码的Verilog实现，用的是改进的BM算法，已在QuautusII9.0上调试通过-rs decoder verilog
rs_dec_enc_latest.tar
- RS encoder decoder on vhdl
RS_Verilog
- there is a verilogHDL about RS decoder.
RSdecFlash_100722
- RS(511,495) decoder for NAND flash controller,decoding steps: (1)syndrome (2)Berlekamp-Massey (3)chien (4)forney
Verilog_RS_31_19
- RS Decoder (31,19,6) v1.1
RS
- RS译码器的设计，使用RS码设计的译码器-RS decoder design, the use of RS code decoder design
RS
- RS译码器的设计源程序--verilog HDL实现-Design of the RS decoder source code-- Verilog HDL
ug_rs-compiler
- altera RS编译码器datasheet-the datasheet of the rs encoder and decoder of altera
(255_223)-RS-decoder
- 使用VHDL实现（255,233）的RS硬件译码器，详细地介绍了(255，223)RS码硬件译码器的实现流程，并且分析了影响处理速率提高的瓶颈因素，采用RiBM算法实现译码-Use VHDL (255,233) RS hardware decoder, a detailed descr iption of the (255,223) RS code hardware decoder implementation process, and analyze the bottleneck factor
RS(204,188)译码器的设计
- RS(204,188)译码器说明 原文件： rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_po