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my_audio
- 我写的基于2410的音频播放的程序，采用c/s结构，pc客户端上传音频流，服务器端建立帧缓冲区接收，并播放出来-I wrote based on the 2410 Audio Player procedures adopted c / s structure, pc client uploads audio streams, the server-frame buffer zone established to receive and broadcast
ADC_DAC
- This example streams input from a ADC source to a DAC. An analog signal is acquired block-by-block into SDRAM from the ADC (an AD9244 in this example). The frames are then output with a one-frame delay to the DAC (an AD9744 in this example). I
mp3play
- 非常适合内嵌式mp3播放,例如控制台!注意看压缩包里readme.doc 详细过程,在ARM及MIPS下通过 新建一个 wce application,选择 a simple windows ce application 在 1.tool->options->directories>include files里包含必要的头文件 D:\\WINCE500\\pubilc\\directx\\SDK\\INC D:\\WINCE500\\pubilc\\com
fixed-pointDSPonmp3
- 根据TMS320C55XX系列的DSP在语音信号数字处理方面的强大能力，本文介绍一种采用这种 DSP与高性能立体声音频解码芯片TLV320 AIC23相结合的MP3解码器系统的设计。实验证明该系统可以顺利实现MP3数据流的上传与下载，高质量完成 MP3的解码与播放 。-According to TMS320C55XX series of DSP in the digital voice signal processing capabilities, this paper introduces a
seqdet
- 对串行输入的数据流进行检测的ＶＥＲＩＬＯＧ源代码-On the serial input data streams to detect the Verilog source code
ss_pcm
- It was tested on a XESS XCV800 board interfacing to a proprietary device with a TI DSP, exchanging PCM streams in both directions.
Splitter
- Splitter file to be used to split altera avalon st video stream into two avalon st streams.
WindowsCE.NET_USB_Driver_develop
- 本视频为WindowsCE.NET USB驱动开发的基础视频，通过操作来讲解如何开发USB驱动和其他的流驱动程序。特别适合做Wince驱动开发人员的入门资料，压缩文件中还给出了USB驱动的实例代码。-This video is WindowsCE.NET USB-driven basis for the development of video, through the operation to explain how to develop USB drivers and other strea
cf_cordic_latest.tar
- 一个基于哈弗曼编码的解码器，用于jpeg格式的图片的解码，以及音频流解码。-Huffman code is used in the most streaming applications. I have written a Huffman decoder for jpeg pictures. For audio or other data streams the code have to adapt.
data_transmission
- 并行数据流转换为一种特殊的串行数据流 重点在通信协议的实现上 注意同一时钟驱动几个信号时，若信号需要分别使用跳变沿或电平有效，那么分别用时钟的不同沿进行驱动-Parallel data streams into a special kind of serial communication protocol data stream focuses on the realization of the same clock-driven attention to a few signals,
811199
- Stream-Oriented FPGA Computing in the Streams-C High Level Language
IIC
- WinCE下的IIC驱动，此驱动为流接口驱动，采用中断方式。-I2C (logical) MDD/PDD Streams interface driver
14.pdf.tar
- Abstract—2×2 unitary precoding based on receiver feedback is applied alongside spatial multiplexing at the base station in HSDPA (D-TxAA) when the mobile terminal supports MIMO transmissios [1]. This precoding will influence achievable sumrate
ImplementationofHighSpeedUpDownConversionFIRFilter
- 为了对FPGA 的资源占用量最小，以便实现 片上系统(SoC)设计，充分利用了上下变频过程中I，Q 数据流的特点，仅用一套滤波器运算单元分时复用对I，Q 滤波，同时详细研究了滤波器的转置结构和位平面结构对FPGA资源占用量的差别。-Benefiting from the characteristics of I and Q data streams in the converter。 one set of computation units is multiplexed to fil
bit_stuffer
- Bit stuffing is used for various purposes, such as for bringing bit streams that do not necessarily have the same or rationally related bit rates up to a common rate, or to fill buffers or frames. The location of the stuffing bits is communicated to
ASI_IN1_and_ASI_OUT1
- 这是对于从卫星接收下来的TS流，有两路流，对其选择，其中包括同步模块，PCR校正模块，码率调整模块-This is received from the satellite down for the TS stream, there are two streams of their choice, including the synchronization module, PCR correction module, rate adjustment module
Encoder1
- encode of aes arith" it describer how to encode streams and something.. if you want to acknowlegde about-encode of aes arith" it describer how to encode streams and something.. if you want to acknowlegde about
TX
- In data transmission and telecommunication, bit stuffing (also known—uncommonly—as positive justification) is the insertion of noninformation bits into data. Stuffed bits should not be confused with overhead bits. Bit stuffing is used for variou
MEB-Video-Streaming-Demo_072911
- PIC32媒体扩展版DEMO程序，一个视频流的例子-PIC32 media expanded version of the DEMO program, an example of video streams
Demultiplexing-200-MHz-Data-Streams
- Modern serial data protocols (e.g., FireWire, SONET, ATM, T4) sometimes require clocks that are faster than maximum FPGA global clock speeds. To solve this problem, the incoming clock (200 MHz in the example below) can be used to demultiple