搜索资源列表
SATA_Verification_IP-SystemVerilog
- SATA Verification IP - SystemVerilog,是使用FPGA做的sata接口部分，是一篇文档-SATA Verification IP- SystemVerilog, is to use FPGA to do sata interface part, is a document
ASIC_and_FPGA_Verification
- ASIC/FPGA验证经典资料，英文版，希望大家可以有所借鉴。-ASIC/FPGA verification classic information, in English, I hope that we can learn from there.
cisco_e
- 有关cisco用e语言验证的验证代码和使用说明-cisco e language verification
mini-uart
- Verilog实现mini-uart，代码经过FPEG验证，含文档及流程图。-Verilog implementation mini-uart, code FPEG After verification, including documentation and flow chart.
spi_vhdl_source
- SPI的VHDL程序，经过quartus验证的，不错！-SPI of the VHDL program, after verification quartus, yes!
DW8051(Verilog)
- 51单片机IP核源码，可以在fpga实现，并进行仿真与验证-51 single-chip IP nuclear source, you can achieve the fpga, and simulation and verification
systemverilog
- system verilog 是国际流行的设计和验证语言，根据语言的特点分为两部分:for设计和for验证。另外一种书是介绍如何应用system verilog, 如果你要用syntem verilog, 推荐先读一下。-system verilog is popular hardware design and verification language. The languange compose of two part: systemverilog for desin , system ve
UARTipcore
- 这是一个关于UART的IP核，用VHDL写的。经过本人的鉴证，非常实用并且写的非常好。-This is one of the IP core on the UART, using VHDL written. After my verification, very practical and very well written.
Chapter11-13
- 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个
speaker_verification
- Speaker verification codes
SystemVerilogEventRegionsRaceAvoidanceGuidelines.r
- The IEEE1800 SystemVerilog Standard includes new event regions primarily added to reduce race conditions between verification code and SystemVerilog designs. The new regions also facilitate race-free Assertion Based Verification (ABV). This pap
Systemverilog_for_Verification
- Systemverilog for Verification源代码，包括arb_if,atm_virt_if,multi_if_port等-code of Systemverilog for Verification,
Sdram_Control_2Port
- 双端口SDRAM控制器，将SDRAM虚拟成两个端口，已经在ALTER DE2开发板的硬件上验证通过，采用Verilog HDL语言编写。-Dual-port SDRAM controller, SDRAM virtual into two ports, have ALTER DE2 development board hardware verification by using the Verilog HDL language.
fft(VHDL)
- 该源码是fft的VHDL实现，通过FPGA下载验证通过-The source is the fft of the VHDL implementation, through verification by FPGA download
SYSTEM-ON-A-CHIP-Verification
- 芯片设计SoC验证书籍 SYSTEM-ON-A-CHIP-Verification-SYSTEM-ON-A-CHIP-Verification
Constraint-Based-Verification
- 系統化驗証方法及實例探討Assertion, Constraint synthesis-Electronic Design complexity getting higher, the verification work needs to be fully understood
ASIC.and.FPGA.Verification.A.Guide.to.Component.Mo
- ASIC的FPGA模型设计，VHDL版 英文原版书籍-ASIC.and.FPGA.Verification.A.Guide.to.Component.Modeling.Morgan.Kaufmann
SystemVerilogforVerification2ndEd
- ebook for System Verilog for Verification second edition
VerificationMethodologyManualforSystemVerilog
- Verification Methodology Manual for SystemVerilog
sv-for-Verification-2nd
- System Verilog for Verification, 2nd Edition.非常经典的资料，供IC开发的人员作自测平台或者验证的人员使用-System Verilog for Verification, 2nd Edition. Very classic information for IC self-test platform for the development of personnel for use by or verification