搜索资源列表
verilog
- 是几个用Verilog HDL语言编写的源代码(里面包括实现滤波器等),对想学习这个语言的朋友很有帮助!
fir_hdl.rar
- 一个 FIR 滤波器的 verilog 实现, 与 matlab 产生的 reference code 相互验证。,Verilog a FIR filter to achieve, with the reference code generated by matlab mutual authentication.
filter_verilog.rar
- 用verilog实现的低通滤波器,输入输出精度为64位,并附有测试程序。,Use verilog to achieve a low-pass filter, input and output accuracy of 64, together with testing procedures.
fir.rar
- fir滤波器,Verilog语言写的,容易看懂,fir filter, Verilog language written in easy to understand
FIRde-verilog-shixian
- 有符号DA算法的FIR滤波器的Verilog实现-A symbol of the algorithm of DA FIR filters Verilog realized
butterworth_iir_verilog.rar
- 基于butterworth的iir滤波器的verilog代码,已经通过测试。,err
costas的verilog程序
- costas的verilog程序,包含乘法器,DDS,鉴相器,环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
18a
- 匹配滤波器设计,VERILOG实现的,比较好的哦-Matched filter design, VERILOG implementation, and better oh
filter
- 如何利用verilog设计数字滤波器 包含低通滤波器,带通滤波器,高通滤波器.-how to design a digit filter with Verilog
LMS_filter
- verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
verilog-example
- 4位并行乘法器 4位超前加法器 ALU 计数器 滤波器 全加器 序列检测器 移位器-failed to translate
16_FIR
- 16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有限频率响应滤波器!-16-order FIR filter- this design language VERILOG HDL serial DA algorithm limited frequency response of 16-order filter!
verilog.DA.FIR..
- 用verilog写的16阶串行DA算法FIR滤波器-Verilog written by 16-order FIR filter serial DA algorithm
fir
- Verilog编的fir滤波器,可以自己输入参数序列,产生滤波波形-Verilog compiled fir filter, input parameters can be their own sequence, resulting in filtered waveforms
cic_intp_64_four
- 4阶CIC内插滤波器,内插系数64,Verilog版本,数字下变频-4-order interpolating CIC filter interpolation factor of 64, Verilog version of the digital down-conversion
fir_dec3
- FIR抽取滤波器,抽取系数3,Verilog版本,数字下变频-FIR decimation filter, extraction coefficient of 3, Verilog version of the digital down-conversion
11orderFIR
- 11阶FIR数字滤波器,Verilog版本,数字下变频,适合初学-11-order FIR digital filter, Verilog version of the digital down conversion, suitable for beginners
verilog
- 经典Verilog源代码,包括加法器,滤波器和qpsk的设计-Classic Verilog source code, including adders, filters and qpsk design, etc. ...
Verilog的135个经典设计实例
- Verilog的135个经典设计实例,部分摘录如下:【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】(7,4)循环码纠错译码器【例 12.10】(7,4)线性分组码译码器【例
fir滤波器
- FIR滤波器,verilog编写,可以正常使用(FIR filter, written by verilog, can be used normally, very good)