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freerisc8_11.zip
- 8位RISC CPU的VERILOG编程 SOURCECODE,8 RISC CPU VERILOG programs SOURCECODE
使用verilog hdl实现16位的cpu设计
- 实现16位的cpu设计 内容使用verilog hdl实现，具体的实现步骤方法，都已经写到文档里面去了！,To achieve 16-bit design of the contents of the cpu using verilog hdl achieve, the specific methods to achieve these steps have already been written inside the document went to!
pipelined-mips-cpu
- 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
RISC8.ZIP
- verilog RISC8 cpu CORE 8位RISC CPU 内核源码（VERILOG 版）-verilogRISC8 cpu CORE8-bit RISC CPU core source (VERILOG version)
CPU
- verilog编写CPU： 1. 哈佛存储器结构，大端格式； 2. 类MIPS精简指令集，支持子程序调用和软中断； 3. 实现了乘除法； 4. 五级流水线，工作频率可达80MHz（每个时钟周期一条指令，不计流水线冲突）。 -MIPS like CPU using verilog
CPU
- 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
cpu
- verilog编写的简单的CPU，用于参考，已经过仿真-verilog prepared by a simple CPU, for reference, has been simulation
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
CPU
- 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
RISC
- hrisc cpu，为何只有vhdl选择呢？大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the Verilog ah
riscpu
- 一个32位微处理器的verilog实现源代脉,采用5级流水线和cache技术.-a 32 Microprocessor verilog achieve pulse generation sources, used five lines and cache technology.
TINY3
- verilog 编写的tiny cpu 代码，可实现简单的指令和计算-Verilog prepared tiny cpu code, can be simple instructions and the calculation
mipsCPU
- MIPS CPU tested in Icarus Verilog
KD_CPU_src
- verilog语言写的8位CPU源代码，基本的算术运算和逻辑运算，对于学习计算机原理和verilog语言都有良好的效果-Verilog Language Writing 8-bit CPU source code, the basic arithmetic operations and logic operations, the study of computer principles and Verilog language has good results
Microprocessor
- 精通verilog HDL语言编程的一个不错的cpu 代码-Verilog HDL language proficiency of a good cpu code
cpu(FinalWithYS)
- verilog实现的八位CPU，包括乘法、除法以及多种寻址方式。代码中包括测试模块，可以直接在试验箱上运行。-verilog to achieve the eight CPU, including multiplication, division, as well as addressing a variety of ways. Code, including test modules, can be run directly in the chamber.
CPU
- verilog实现的一个简单的CPU，大家可下载去瞅瞅啊-verilog to achieve a simple CPU, you can download to Chou Chou ah
8bit_RISC_CPU_RTL_Code
- 8位RISC CPU 内核源码(VERILOG版)-8 bit RSIC CPU RTL code(Verilog)
CPU
- 一个完整的流水CPU设计，quartus平台，Verilog实现-CPU design a complete water, quartus platform, Verilog realization
cpu
- cpu design in verilog