搜索资源列表
-
0下载:
用verilog实现的低通滤波器,输入输出精度为64位,并附有测试程序。,Use verilog to achieve a low-pass filter, input and output accuracy of 64, together with testing procedures.
-
-
0下载:
低通滤波器在QUARTUS7.0开发环境下的文本与框图结合的实现方法的源代码-Low-pass filter QUARTUS7.0 development environment in the text and diagram combination of methods to achieve source code
-
-
1下载:
基于DSPbuilder搭建的DDC,里面包括CIC滤波器,FIR低通滤波器,HB半带滤波器,NCO等,实现了GC5016芯片的功能-DSPbuilder erected based on DDC, which include the CIC filter, FIR low-pass filter, HB half-band filter, NCO, etc. to achieve the function of the GC5016 chip
-
-
0下载:
DDS的工作原理是以数控振荡器的方式产生频率、相位可控制的正弦波。电路一般包括基准时钟、频率累加器、相位累加器、幅度/相位转换电路、D/A转换器和低通滤波器(LPF)。频率累加器对输入信号进行累加运算,产生频率控制数据X(frequency data或相位步进量)。相位累加器由N位全加器和N位累加寄存器级联而成,对代表频率的2进制码进行累加运算,是典型的反馈电路,产生累加结果Y。幅度/相位转换电路实质上是一个波形寄存器,以供查表使用。读出的数据送入D/A转换器和低通滤波器。-DDS works
-
-
0下载:
在FPFA上实现低通滤波,使用VERILOG编写-In FPFA to achieve low-pass filter, using VERILOG write
-
-
0下载:
用verilog实现一个8阶的改进串行FIR低通滤波器,输入数据位宽为12比特,经符号扩展后变为13比特。-With verilog order to achieve an improvement of 8 serial FIR low-pass filter, the input data bit width of 12 bits by sign extension into a 13-bit after.
-
-
0下载:
low pass FIR filter programmed by Verilog, you can change the coefficients in the program to achieve different response
-
-
0下载:
以VERILOG语言描绘的用TLC549和TLC5615的数字低通滤波器的程序-VERILOG language used to describe the TLC549 and TLC5615 digital low pass filter process
-
-
0下载:
verilog的32阶FIR低通滤波器描述-verilog 32-order FIR low-pass filter described
-
-
0下载:
verilog HDL 编的8阶八位输入的低通滤波器-verilog HDL code of 8 eight-order low-pass filter input
-
-
0下载:
基于Verilog的低通滤波器的设计与实现-Based on the Verilog low-pass filter of design and implementation
-
-
1下载:
用Verilog语言设计的一个数字FIR低通滤波器,很实用,通过modelsim仿真成功-Verilog language to design a digital FIR low-pass filter, very practical, through modelsim simulation success
-
-
0下载:
用Verilog HDL编写的FIR低通滤波器。FIR低通滤波器采用8阶串行方式实现。-Written using Verilog HDL FIR low-pass filter. FIR low-pass filter 8-order serial.
-
-
0下载:
简易FIR低通滤波器的verilog代码-Simple FIR low-pass filter verilog code
-
-
0下载:
用verilog实现带宽可调的低通滤波器-Verilog to achieve the low-pass filter with adjustable bandwidth
-
-
0下载:
使用verilog 编写的128阶低通滤波器,抽头系数可调。-Prepared using verilog-order low-pass filter 128, the tap coefficients adjustable.
-
-
0下载:
本设计是基于FPGA的一个FIR低通滤波器设计,要求使用Verilog语言编写滤波器模块,通过编译和综合,并通过Matlab和modelsim联合仿真验证设计结果。-This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design re
-
-
0下载:
基于fpga的DDS详细设计方案 verilog语言 正弦计算器则对该相位值计算数字化正弦波幅度(芯片一般通过查表得到)。DDS芯片输出的一般是数字化的正弦波,因此还需经过高速D/A转换器和低通滤波器才能得到一个可用的模拟频率信号。-Direct Digital Synthesizer base on fpga
use verilog Sine calculator to calculate the value of the digital phase sine wave amplitu
-
-
0下载:
基于verilog的 FIR低通滤波器的实现(Implementation of FIR low pass filter based on Verilog)
-
-
0下载:
自己写的FIR八戒低通滤波器,仅供参考(Write your own FIR eight quit low-pass filter, for reference only)
-