一个简单的verilog绘图工具，工具向数据库导入电路连接信息，程序通过数据库的信息刷新屏幕，并且向用户导出门级建模的verilog语句-Verilog a simple drawing tools, tools, electrical connections to the database information into the program information through the database to refresh the screen, and exported to th

此程序的功能是对Quartus II软件仿真完成之后，导出的.tbl文件进行matlab画图，画出其时域图和频域图。其中待处理的.tbl文件，我将其进行人工处理，手动删除了无用信息，只剩余时间点、输入信号和输出信号。-The function of this program after the completion of the Quartus II software simulation, export tbl file matlab drawing, draw a diagram of th

licence.dat证书，用于quartus10.0的破解文件-licence.dat certificate for quartus10.0 the crack file

Ezidebug 支持Xilinx，chipscope 寄存器链插入、数据采集和导出、重建testbench和软件仿真验证(Ezidebug supports Xilinx, chipscope register chain insertion, data acquisition and export, reconstruction of testbench and software simulation verification)